VLSI Design and CAD Group

This group researches VLSI design methodology, circuit technology and architecture for future advanced integrated devices. Focusing on timing, power dissipation and reliability that determines chip performance and quality, we are studying system integration, VLSI chip design and CAD algorithms.

VLSI Self Performance Compensation


VLSIs are facing a crucial obstacle that prevents future performance improvement, that is manufacturing variability and environmental fluctuation (supply voltage and temperature) are significantly increasing and affecting VLSI performance. In addition, circuit aging is also becoming a critical design issue for performance variation. This research aims to establish a circuit and design methodology for realizing VLSIs that compensate their performance automatically based on sensed variability and aging information. We are also validating the methodology with chip fabrication and measurement. 

Subthreshold Circuit Design for Ultra Low Power Applications

Sensor network is drawing a lot of attention as a technology for realizing future secure and safe society. Sensor nodes, which compose a sensor network, are required to operate for a long time with power supply whose capacity is limited, such as button and solar cells, and hence ultra low power design is highly demanded. Recently, for such a purpose, subthreshold circuits are proposed. Subthreshold circuit operates at very low supply voltage, and it consumes extremely small power though its speed is very slow. On the other hand, the characteristics of subthreshold circuits are much different from those of normal superthreshold circuits. Therefore new circuit techniques and design methodology are necessary. We are studying for establishing a design methodology tailored for subthreshold circuits and designing VLSI chips for the design methodology validation.

On-chip Small True Random Number Generator


As social infrastructure is constructed on ICT, information security, especially importance of random number is increasing. For encryption, true random number, which has unpredictability and is generated exploiting physical statistical fluctuation, is demanded. However, pseudo random number generators are used instead of true random number generator, and the predictability of random number has not sufficiently assured. This research aims to develop an on-chip small true random number generator, and provides an environment that true random number with unpredictability is easily used for key generation and encryption. We focus on oscillator-based true random number generator that is robust to external perturbation (noise from other circuits and side-channel attack), and study self-tuning of circuit operation to cope with manufacturing and environmental variability and assure quality of random number.

Timing Design Methodology for Nano-scale Generation


In nano-scale VLSIs, manufacturing variability and power supply noise significantly fluctuate circuit performance. To achieve high-speed operation and attain high reliability, a new design methodology is necessary. We are researching measurement, verification, prediction and suppression techniques for power supply noise, and mitigation techniques for manufacturing variability. For noise measurement and validation of noise suppression, we design and measure VLSI chips.

Static timing analysis with a unified approach to manufacturing and environmental variability


VLSI fabrication necessarily involves manufacturing variability. In addition, in actual operating condition, power supply voltage and temperature fluctuate. In current advanced technologies, the impact of these variabilities on circuit performance is significantly increasing, and its estimation before fabrication is getting difficult. This research is developing a timing analysis method that aims at taking both static manufacturing variability and dynamic environmental fluctuation into consideration simultaneously. To realize this, we have developed a gate delay model for large variability and statistical modeling of power supply noise.

Last-modified: 2010-03-20 (Sat) 22:36:35