Dependable VLSI Group

Scaling of integrated circuits has enabled electronics to merge with almost all fields, which in turn offers man kind evermore convenient products and systems dedicated for the ease of life and luxury. Unfortunately, process scaling is accompanied with numerous undesirable phenomenons such as, circuit degradation, sensitivity to radiation, current leakage and so on. Such phenomenons require designers to provide special attention, and also offer opposing solutions. In this research group, students are given the chance to face challenges similar to the ones encountered by designers dealing with cutting edge technologies, to study, design and implement circuits that have the ability to perform unlimited tasks upon reconfiguration, to investigate radiation effect and techniques to mitigate it, and to design and implement mechanisms that grant circuits the ability to heal itself to mitigate degradation and provide a long lasting lifespan.

FRRAry : Flexible Reliability Reconfigurable Array


In this research, we develop circuits (reconfigurable logic) which can change their function according to bit streams of data referred to as configuration information. Upon setting different configuration information, the logic can be reconfigured to perform unlimited tasks. When thinking about reconfigurable architecture design, it is necessary to take into account diversity of functionality, flexibility of interconnect, performance and power consumption, and reliability considerations. Here, we get introduced to the world of fine-grained and coarse-grained reconfigurable architectures, and also, we have the chance to be an active part of the reconfigurable architecture design process leveraging the four considerations mentioned above. Moreover, through out the course of this research, students gain essential hands-on experience in the hardware development process involving design, implementation, pre-silicon verification, layout, post-silicon verification and validation.

Degradation Effects of Circuit


In recent years, degradation effects of circuit such as HCI (Hot Cariier Injection), TDDB (Time Dependence Dielectric Breakdown), NBTI (Negative Bias Temperature Instability) become a more considerable issue. In these effects, NBTI is one of serious aging problem, increasing threshold voltage and leading a timing degradation. NBTI effect has two phases, stress and recovery. Stress means PMOS is active, in other words, gate voltage is negatively biased. In this phase, Vth increases gradually. On the other hand, in recovery phase, which means PMOS is OFF, Vth gradually decreases to its initial value before stress undergoing. In this work, we research and recognize these degradation effects. Moreover, we consider architectures which enable to mitigate circuit delay degradation.

SET Pulse Width Measurement Circuit


As VLSI technology advances, soft error is becoming a serious issue in digital circuit design. Soft error arises when radiation particles collide with Si substrate and electrons/holes charge are induced and collected. When an SET (Single Event Transient), which is a kind of soft error generated in a combinational circuit, propagates to a sequential element and is captured at clock edges, the SET pulse causes an error. Information on the distribution of SET pulse width is eagerly demanded for SET-oriented soft error estimation and suppression because a wider SET pulse more probably causes an error. On the other hand, existing SET pulse width measurement circuits have remaining issues to resolve for obtaining the distribution. This research aims to develop SET pulse width measurement circuit to satisfy the requirements suitable for precise SET pulse width measurement.

Last-modified: 2010-04-07 (Wed) 15:08:22