Selected Publications of Takao ONOYE
Journal Publications

T. Onoye, A. Yamada, I. Arungsrisangchai, M. Tanaka and I. Shirakawa:
"An automatic layout generator for bipolar analog modules," IEICE
Trans.
Fundamentals, vol. E75A, no. 10, pp. 13061314, Oct. 1992.

T. Onoye, T. Masaki, I. Shirakawa, H. Hirata, K. Kimura, S. Asahara, and
T. Sagishima: "Highlevel synthesis of a multithreaded processor for image
generation," IEICE Trans. Fundamentals, vol. E78A, no. 3, pp. 322330,
March 1995.

T. Masaki, Y. Morimoto, T. Onoye, and I. Shirakawa: "VLSI implementation
of inverse discrete cosine transformer and motion compensator for MPEG2
HDTV video decoding," IEEE Trans. Circuits and Systems for Video Technology,
vol. 5, no. 5, pp. 387395, Oct. 1995.

T. Onoye, T. Masaki, Y. Morimoto, Y. Sato, I. Shirakawa, and K. Matsumura:
"Single chip implementation of MPEG2 decoder for HDTV level pictures,"
IEICE Trans. Fundamentals, vol. E79A, no. 3, pp. 330338, March
1996.

T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai: "Single chip
implementation of motion estimator dedicated to MPEG2 MP@HL," IEICE
Trans. Fundamentals, vol. E79A, no. 8, pp. 12101216, Aug. 1996.

T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami: "Voice and telephony
over ATM for multimedia network using shared VCI cell," Journal of Circuits,
Systems and Computers, vol. 7, no. 2, pp. 93110, April 1997.

吉田幸弘，宋宝玉，奥畑宏之，尾上孝雄，白川功:
"組込み用プロセッサの低消費電力化に関する一手法,"
電子情報通信学会論文誌}, vol. J80A, no. 5, pp. 765771, May 1997 (in Japanese).

K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa: "Single
chip implementation of encoderdecoder for low bitrate visual communication,"
Journal of Circuits, Systems and Computers, vol. 7, no. 5,
pp. 441457, Oct. 1997.

T. Masaki, Y. Nakatani, T. Onoye, N. Yamai, and K. Murakami: "Voice
communication on multimedia ATM network using shared VCI cell,"
IEICE Trans. Communications, vol. E81B, no. 2, pp. 340346,
Feb. 1998.
 木村浩三，奥畑宏之，尾上孝雄，白川功，清原督三，鷺島敬之:
"マルチスレッドプロセッサのデータキャッシュ制御方式,"
映像情報メディア学会誌, vol. 52, no. 5, pp. 742749, May 1998
(in Japanese).

G. Fujita, T. Onoye, and I. Shirakawa: "A VLSI architecture for motion
estimation core dedicated to H.263 video coding," IEICE
Trans. Electronics, vol. E81C, no. 5, pp. 702707, May 1998.

H. Okuhata, M.H. Miki, T. Onoye, and I. Shirakawa: "A lowpower DSP
architecture for low bitrate speech codec," IEICE
Trans. Fundamentals, vol. E81A, no. 8, pp. 16161621, Aug. 1998.

M.H. Miki, 藤田玄，尾上孝雄，白川功:
"携帯端末向け低電力H.263 コーデック・コアのVLSI化設計,"
電子情報通信学会論文誌, vol. J81A, no. 10, pp. 13521361,
Oct. 1998 (in Japanese).

H. Fujishima, Y. Takemoto, T. Onoye, and I. Shirakawa: "An
architecture of matrixvector multiplier dedicated to video decoding
and threedimensional computer graphics," IEEE Trans. Circuits and
Systems for Video Technology, vol. 9, no. 2, pp. 306314, March
1999.

B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa:
"Lowpower scheme of NMOS 4phase dynamic logic,"
IEICE Trans. Electronics, vol. E82C, no. 9,
pp. 17721776, Sept. 1999.

J. Fan, G. Fujita, M. Furuie, T. Onoye, I. Shirakawa, and
L. Wu: "Automatic moving object extraction toward compact video
representation," Optical Engineering, vol. 39, no. 2,
pp. 438452, Feb. 2000.

M. Hatanaka, T. Masaki, T. Onoye, and K. Murakami:
"VLSI architecture of switching control for AAL type2 switch,"
IEICE Trans. Fundamentals, vol. E83A, no. 3,
pp. 435441, March 2000.

B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa:
"Lowpower VLSI implementation by NMOS 4phase dynamic logic,"
Trans. IPSJ, vol. 41, no. 4, pp. 899907, April 2000.

J. Fan, J. Yu, G. Fujita, T. Onoye, L. Wu, and I. Shirakawa:
"Spatiotemporal segmentation for compact video representation,"
Signal Processing: Image Communication, vol. 16, no. 6,
pp. 553566, Feb. 2001.

Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa:
"A novel dynamically reconfigurable hardwarebased cipher,"
Trans. IPSJ, vol. 42, no. 4, pp. 958966, April 2001.

W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa:
"3D acoustic image localization algorithm by embedded DSP,"
IEICE Trans. Fundamentals, vol. E84A, no. 6,
pp. 14231430, June 2001.

H. Tsutsui, A. Tomita, S. Sugimoto, K. Sakai, T. Izumi,
T. Onoye, and Y. Nakamura:
"LUTarraybased PLD and synthesis approach based on sum of
generalized complex terms expression,"
IEICE Trans. Fundamentals, vol. E84A, no. 11,
pp. 26812689, Nov. 2001.

R.Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa:
"An embedded zerotree wavelet video coding algorithm with
reduced memory bandwidth requirements,"
IEICE Trans. Fundamentals, vol. E85A, no. 3,
pp. 703713, March 2002.

宋天, 藤田玄, 尾上孝雄, 白川功:
"携帯端末用低消費電力 H.263 Version 2 コーデックコアのVLSI化設計,"
情報処理学会論文誌, vol. 43, no. 4, pp. 11611170,
May 2002 (in Japanese).

H. Okada, A.E. Shiitev, H.S. Song, G. Fujita, T. Onoye, and
I. Shirakawa:
"Error detection by digital watermarking for MPEG4 video coding,"
IEICE Trans. Fundamentals, vol. E85A, no. 6,
pp. 12811288, June 2002.

岡田浩行, 宋学燮, 藤田玄, 尾上孝雄, 白川功:
"電子透かしのMPEG4ビットストリームエラー検出への応用,"
画像電子学会誌,, vol. 31, no. 5, pp. 900908,
Sept. 2002 (in Japanese).

Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba,
T. Onoye, I. Shirakawa:
"Wireless digital video transmission system using IEEE802.11b
PHY with error correctio block based ARQ protocol,"
IEICE Trans. Communications, vol. E85B, no. 10,
pp. 20322043, Oct. 2002.

H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa:
"Performance estimation at architecture level for embedded systems,"
IEICE Trans. Fundamentals, vol. E85A, no. 12,
pp. 26362644, Dec. 2002.

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa:
"Single DSP implementation of realtime 3D sound synthesis algorithm,"
Journal of Circuits, Systems and Computers, vol. 12, no. 1,
pp. 5573, Feb. 2003.

K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye,
T. Chiba, and I. Shirakawa:
"Object sharing scheme for heterogenous environment,"
IEICE Trans. Fundamentals, vol. E86A, no. 4, pp. 813821,
April 2003.

T. Okamoto, T. Yuasa, T. Izumi, T. Onoye, and Y. Nakamura:
"Design tools and trial design for PCAChip2,"
IEICE Trans. Information and Systems,
vol. E86D, no. 5, pp. 868871, May 2003.

N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa:
" Embedded implementation of acoustic field enhancement for stereo
sound sources,"
IEEE Trans. Consumer Electronics,
vol. 49, no. 3, pp. 737741, Aug. 2003.

宋学燮, 岡田浩行, 藤田玄, 尾上孝雄, 白川功:
"MPEG4動画像符号化向けハイブリッドエラー隠蔽方式,"
画像電子学会誌, vol. 32, no. 5, pp. 609620, Sept. 2003.

小谷章夫, 小山至幸, 密山幸男, 尾上孝雄:
"低解像度表示デバイス向けフォントLCFONTの重心および可読性の評価,"
画像電子学会誌,
vol. 32, no. 5, pp. 621628, Sept. 2003.

M. Kimura, M.H. Miki, T. Onoye, and I. Shirakawa:
"Implementation of Java accelerator for high performance embedded
systems,"
IEICE Trans. Fundamentals,
vol. E86A, no. 12, pp. 30793088, Dec. 2003.

岡田勉, 内田翼, 尾上孝雄, 白川功:
"次世代GNSS受信機用信号処理機構とそのVLSI化設計,"
電子情報通信学会論文誌, vol. J86A, no. 12, pp. 14171425, Dec. 2003.

T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa:
"Embedded 3D sound movement system based on feature extraction of
headrelated transfer function,"
IEEE Transactions on Consumer Electronics,
vol. 51, no. 1, pp. 262267, Feb. 2005.

Y. Mituyama, M. Kimura, T. Onoye, I. Shirakawa:
"Architecture of IEEE802.11i cipher algorithms for embedded systems,"
IEICE Trans. Fundamentals,
vol. E88A, no. 4, pp. 899906, April 2005.

K. Tsujino, K. Furuya, W. Kobayashi, T. Izumi, T. Onoye, and
Y. Nakamura:
"Design of realtime 3D sound processing system,"
IEICE Trans. Information and Systems,
vol. E88D, no. 5, pp.954962, May 2005.

A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa:
"Desing of Ogg Vorbis decoder system for embedded platform,"
IEICE Trans. Fundamentals,
vol. E88A, no. 8, pp. 21242130, Aug. 2005.

藤田玄, 尾上孝雄, 白川功:
"MPEG4向け高精度動き検出コアのVLSI化設計,"
電子情報通信学会論文誌,
vol. J88A, no. 11, pp. 12821291, Nov. 2005.

Z. Guo, Y. Nishikawa, R.Y. Omaki, T. Onoye, and I. Shirakawa:
"A lowcomplexity FEC assignment scheme for Motion JPEG2000 over
wireless network,"
IEEE Trans. Consumer Electronics,
vol. 52, no. 1, pp. 8186, Feb. 2006.

M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa:
"WCDMA channel codec by configurable processors,"
Journal of Intelligent Automation and Soft Computing,
vol.13, no. 3, pp. 318330, March 2006.

H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and
Y. Nakamura:
"Design framework for JPEG2000 system architecture,"
Journal of Intelligent Automation and Soft Computing,
vol. 13, no. 3, pp. 331343, March 2006.

G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa:
"Realtime human object extraction method for mobile systems based on
color space segmentation,"
IEICE Trans. Fundamentals,
vol. E89A, no. 4, pp. 941949, April 2006.

小谷章夫, 種村嘉高, 密山幸男, 朝井宣実, 中村安久, 尾上孝雄:
"ポテンシャルエネルギーを用いた文字重心位置取得手法,"
画像電子学会誌, vol. 35, no. 4, pp.296305, Sept. 2006.

K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi: "An
energyefficient architecture of wireless home network based on MAC
broadcast and transmission power control,"
IEEE Trans. Consumer Electronics, vol. 53, no. 1, pp. 124130, Feb. 2007.

K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura:
"Efficient 3D sound movement with timevarying IIR filters,"
IEICE Trans. Fundamentals, vol. E90A, no. 3, pp. 618624,
March 2007.

Y. Ogasahara, M. Hashimoto, and T. Onoye:
"Quantitative prediction of onchip capacitive and inductive crosstalk
noise and tradeoff between wire cross sectional area and inductive
crosstalk effect,"
IEICE Trans. Fundamentals, vol. E90A, no. 4, pp. 724731, April 2007.

K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura:
"Automatic filter design for 3D sound movement in embedded
applications,"
Acoustical Science and Technology, vol. 28, no. 4, pp. 219229,
July 2007.

M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto,
I. Keshi, and I. Shirakawa:
"Design and implementation of home network protocol for appliance
control based on IEEE 802.15.4,"
International Journal of Computer Science and Network Security,
vol. 7, no. 7, pp. 2030, July 2007.

Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye:
"Validation of a fullchip simulation model for supply noise and delay
dependence on average voltage drop with onchip delay measurement,"
IEEE Trans. Circuits and SystemsII: Express Briefs,
vol. 54, no. 10, pp. 868872,October 2007.

N. Iwanaga, T. Matsumura, A. Yoshida, W. Kobayashi, and T. Onoye:
"Embedded system implementation of sound localization in proximal
region,"
IEICE Trans. Fundamentals
vol. E91A, no. 3, pp. 763771,March 2008.

Y. Ogasahara, M. Hashimoto, and T. Onoye: "Measurement
and analysis of inductive coupling noise in 90nm global
interconnects,"
IEEE Journal of SolidState Circuits,
vol. 43, no. 3, pp. 718728,March 2008.

R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye:
"Implementation of multiagent object attention system based on
biologically inspired attractor selection," IEICE Trans. Fundamentals,
vol. E91A, no. 10, October 2008.

Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and
I. Shirakawa: "Areaefficient reconfigurable architecture for media
processing," IEICE Trans. Fundamentals, vol. E91A, no. 12,
pp. 36513662, December 2008.

S. Abe, M. Hashimoto, and T. Onoye: "Clock skew evaluation considering
manufacturing variability in meshstyle clock distribution," IEICE
Trans. Fundamentals, vol. E91A, no. 12, pp. 34813487, December
2008.

T. Masuzaki, H. Tsutsui, Q.M. Vu, T. Onoye, and Y. Nakamura: "JPEG2000
highspeed SNR progressive decoding scheme," International Journal of
Computer Science and Network Security, vol. 9, no. 1, pp. 6268,
January 2009.

K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "An
experimental study on bodybiasing layout style focusing on area
efficiency and speed controllability," IEICE Trans. Electronics,
vol. E92C, no. 2, pp. 281285, February 2009.

増崎隆彦, 筒井弘, 尾上孝雄, 水野雄介, 佐々木元, 中村行宏: "シングルタイ
ル JPEG2000 コーデックのシステム構成," 画像電子学会誌, vol. 38, no. 3,
pp. 296304, May 2009.

Y. Ogasahara, M. Hashimoto, T. Onoye: "All digital ringoscillator
based macro for sensing dynamic supply noise waveform," IEEE Journal
of SolidState Circuits, vol. 44, no. 6, pp. 17451755, June 2009.

H. Sugano, T. Masuzaki, H. Tsutsui, T. Onoye, H. Ochi, and
Y. Nakamura, "Efficient memory organization framework for JPEG2000
entropy codec," IEICE Trans. Fundamentals, vol. E92A, no. 8,
pp. 19701977, August 2009.

畠中理英, 達可敏充, 渡邊賢治, 尾上孝雄: "透過減衰を考慮した無線ホーム
ネットワーク向け位置推定," 情報処理学会論文誌, vol. 50, no. 8,
pp. 18351844, August 2009.

H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Tradeoff
analysis between timing error rate and power dissipation for adaptive
speed control with timing error prediction," IEICE
Trans. Fundamentals, vol. E92A, no. 12, pp. 30943102, December
2009.

K. Shinkai, M. Hashimoto, and T. Onoye: "Prediction of selfheating in
short intrablock wires," IEICE Trans. Fundamentals, vol. E93A,
no. 3, pp. 583594, March 2010.

渡邊賢治, 達可敏充, 畠中理英, 尾上孝雄: "屋内位置推定システムのための間
取り推定手法," Journal of Signal Processing, vol. 14, no. 3,
pp. 231242, May 2010.

密山幸男, 高橋一真, 今井林太郎, 橋本昌宜, 尾上孝雄, 白川功: "メディア処
理向け再構成可能アーキテクチャでの動画像復号処理の実現," 電子情報通信学
会論文誌, vol. J93A, no. 6, pp. 397413, June 2010.

H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Transistor
variability modeling and its validation with ringoscillation
frequencies for bodybiased subthreshold circuits," IEEE Transactions
on VLSI Systems, vol. 18, no. 7, pp. 11181129, July 2010.

大原一人, 芥子育雄, 尾上孝雄: "映像コンテンツ同時閲覧のための負荷適応デ
コーダ制御手法," 画像電子学会誌, vol. 39, no. 6, pp. 10951103,
November 2010.

M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi: "3D
sound rendering for multiple sound sources based on Fuzzy clustering,"
IEICE Trans. Fundamentals, vol. E93A, no. 11, pp. 21632172, November
2010.

R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye: "Measurement circuits
for acquiring SET pulse width distribution with subFO1inverterdelay
resolution," IEICE Trans. Fundamentals, vol. E93A, no. 12,
pp. 24172423, December 2010.
International Conferences

T. Onoye, A. Yamada, I. Arungsrisangchai, M. Tanaka and I. Shirakawa: "An
automatic layout generator for bipolar analog modules," in Proc. IEEE
Int'l Symposium on Circuits and Systems, pp. 22642267, May 1992.

T. Onoye, T. Masaki, H. Hirata, K. Kimura, S. Asahara, T. Sagishima, I.
Shirakawa, S. Tsukiyama, and S. Shinoda: "Highlevel synthesis of multithreaded
processor based image generator," in Proc. IEEE Int'l Symposium on Industrial
Electronics, pp. 4752, May 1994.

K. Kimura, H. Hirata, T. Kiyohara, S. Asahara, T. Sagishima, T. Onoye,
and I. Shirakawa: "Evaluation method of microarchitecture for multithreaded
processor," in Proc. IEEE Int'l Symposium on Industrial Electronics,
pp. 5358, May 1994.

T. Sagishima, K. Kimura, H. Hirata, T. Kiyohara, S. Asahara, T. Onoye,
and I. Shirakawa: "Multithreaded processor for image generation," in Proc.
IEEE Int'l Symposium on Circuits and Systems, pp. 4.2314.234, May
1994.

T. Onoye, T. Masaki, H. Hirata, K. Kimura, S. Asahara, T. Sagishima, I.
Shirakawa, S. Tsukiyama, and S. Shinoda: "Highlevel synthesis of a multithreaded
processor for image generation: design and simulation" in Proc. European
Simulation Multiconference, pp. 948953, June 1994.

T. Onoye, T. Masaki, S. Asahara, T. Sagishima, I. Shirakawa, S. Tsukiyama,
and S. Shinoda: "Design of multithreaded processor dedicated to image generation:
Highlevel synthesis" in Proc. Joint Technical Conference on Circuits/Systems,
Computers, Communication, pp. 689694, July 1994.

T. Onoye, Y. Morimoto, T. Masaki, and I. Shirakawa: "Design of inverse
DCT unit and motion compensator for MPEG2 HDTV decoding," in Proc. IEEE
AsiaPacific Conference on Circuits and Systems, pp. 608613, Dec.
1994.

T. Masaki, Y. Morimoto, T. Onoye, and I. Shirakawa: "Specific functional
macrocells for MPEG2 singlechip HDTV decoder," in Proc. Joint Technical
Conference on Circuits/Systems, Computers, Communication, pp. 499502,
July 1995.

T. Masaki, Y. Morimoto, Y. Sato, T. Onoye, and I. Shirakawa: "Singlechip
VLSI decoder for MPEG2 MP@HL," in Proc. Synthesis and System Integration
of Mixed Technologies, pp. 211218, Aug. 1995.

T. Masaki, Y. Morimoto, Y. Sato, T. Onoye, and I. Shirakawa: "Singlechip
implementation of MPEG2 decoder dedicated to MP@HL," in Proc. Int'l
Conference on VLSI and CAD, pp. 2528, Oct. 1995.

T. Onoye, M. Takatsu, G. Fujita, I. Shirakawa, and K. Matsumura: "A VLSI
implementation of MPEG2 motion estimation algorithm based on macroblock
clustering," in Proc. Int'l Conference on VLSI and CAD, pp. 3336,
Oct. 1995.

T. Onoye, T. Masaki, Y. Morimoto, Y. Sato, and I. Shirakawa: "HDTV level
MPEG2 video decoder VLSI," in Proc. IEEE TENCON '95 on Microelectronics
and VLSI, pp. 468471, Nov. 1995.

T. Onoye, G. Fujita, M. Takatsu, and I. Shirakawa: "Implementation of MPEG2
MP@HL motion estimator," in Proc. Int'l Conference on Neural Networks
and Signal Processing, pp. 15901593, Dec. 1995.

T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi,
and S. Tsukiyama: "VLSI implementation of hierarchical motion estimator
for MPEG2 MP@HL," in Proc. IEEE Custom Integrated Circuits Conference,
pp. 351354, May 1996.

T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi,
and S. Tsukiyama: "A VLSI architecture of MPEG2 MP@HL motion estimator,"
in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 664667,
May 1996.

G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa: "Single
chip MPEG2 MP@ML motion estimator," in Proc. Int'l Technical Conference
on Circuits/Systems, Computers and Communications, pp. 286289, July
1996.

K. Miyanohana, G. Fujita, T. Onoye, I. Shirakawa, and N. Yamai: "VLSI architecture
for very low bitrate video encoder core," in Proc. Int'l Technical Conference
on Circuits/Systems, Computers and Communications, pp. 294297, July
1996.

T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura: "A single
chip motion estimator dedicated to MPEG2 MP@HL," in Proc. European Signal
Processing Conference, pp. 14791482, Sept. 1996.

T. Komura, M. Oka, T. Fujiwara, T. Onoye, T. Kasami, and S. Lin: "VLSI
architecture of a recursive maximum likelihood decoding algorithm for a
(64,35) subcode of the (64,42) ReedMuller code," in Proc. IEEE Int'l
Symp. Information Theory and Its Applications, pp. 709712, Sept. 1996.

Y. Yoshida B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa: "Lowpower
consumption architecture for embedded processor," in Proc. 2nd International
Conference on ASIC, pp. 7780, Oct. 1996.

K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa: "Implementation of
very low bitrate video encoder core," in Proc. 2nd International Conference
on ASIC, pp. 131134, Oct. 1996.

K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa: "VLSI implementation
of edge detector and vector quantizer for very low bitrate video encoding,"
in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS
'96), pp. 480483, Nov. 1996.

G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura: "Implementation
of halfpel precision motion estimator for MPEG2 MP@HL," in Proc. IEEE
Region 10 International Conference on Digital Signal Processing Applications
(TENCON '96), pp. 949954, Nov. 1996.

T. Onoye and I. Shirakawa: "VLSI architecture for MPEG2 MP@HL codec," in
Proc. Int'l Workshop on Logic and Architecture Synthesis, pp. 251258,
Dec. 1996.

K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa: "VLSI
implementation of single chip encoder/decoder for low bitrate visual communication,"
in Proc. IEEE Custom Integrated Circuits Conference, pp. 229232,
May 1997.

G. Fujita, T. Onoye, and I. Shirakawa: "A new motion estimation core dedicated
to H.263 video coding," in Proc. IEEE International Symposium on Circuits
and Systems, pp. 11611164, June 1997.

T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami: "Multimedia ATM network
using shared VCI cell and VLSI implementation of rerouting node," in Proc.
IEEE International Symposium on Circuits and Systems, pp. 27932796,
June 1997.

T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami: "Fellow cell switching
for voice communication on multimedia ATM network and its VLSI impelementation,"
in Proc. Int'l Technical Conference on Circuits/Systems, Computers and
Communications, pp. 12191222, July 1997.

H. Fujishima, Y. Takemoto, T. Onoye, and I. Shirakawa: "Mediaprocessor
architecture unified for video coding and 3D graphics," in Proc. Int'l
Technical Conference on Circuits/Systems, Computers and Communications,
pp. 12231226, July 1997.

M. H. Miki, G. Fujita, T. Onoye, S. Tsukiyama, and I. Shirakawa: "Lowpower
H.263 video codec dedicated to mobile computing," in Proc. ACM/IEEE
Int'l Symp. Low Power Electronics Design, pp. 7679, Aug. 1997.

Y. Yoshida, B.Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa: "An object
code compression approach to embedded processors," in Proc. ACM/IEEE
Int'l Symp. Low Power Electronics and Design, pp. 265268, Aug. 1997.

M.H. Miki, G. Fujita, T. Kobayashi, T. Onoye, and I. Shirakawa: "A lowpower
H.263 video codec core dedicated to mobile computing," in Proc. IFIP
Int'l Conf. Very Large Scale Integration, pp. 314, Aug. 1997.

H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi: "A
unified mediaprocessor architecture for video coding and computer graphics,"
in Proc. Int'l Workshop on SyntheticNatural Hybrid Coding and Three
Dimensional Imaging, pp. 253256, Sept. 1997.

Y. Yoshida, T. Onoye, I. Shirakawa, and N. Kubo: "Simulation in low power
embedded processor design," in Proc. European Simulation Symposium,
pp. 557561, Oct. 1997.

T. Onoye, G. Fujita, H. Okuhata, M.H. Miki, and I. Shirakawa:
"Lowpower implementation of H.324 audiovisual codec dedicated to
mobile computing," in Proc. ACM/IEEE Asia and South Pacific Design
Automation Conference, pp. 589594, Feb. 1998.

G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa:
"Implementation of H.324 audiovisual codec for mobile
computing," in Proc. IEEE Custom Integrated Circuits
Conference, pp. 193196, May 1998.

H. Okuhata, M.H. Miki, T. Onoye, and I. Shirakawa: "A low power DSP
core architecture for low bitrate speech codec," in
Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal
Processing, pp. 31213124, May 1998.

Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and
I. Shirakawa: "VLSI implementation of function module for texture
mapping and motion compensation," in Proc. Int'l Technical
Conference on Circuits/Systems, Computers and Communications,
pp. 179182, July 1998.

R.Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa: "Implementation of
DWT and EZW cores for a bitratescalable video coder," in
Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 221224, July 1998.

H. Fujishima, Y. Takemoto, T. Onoye, and I. Shirakawa:
"Matrixvector multiplier for natural/synthetic hybrid video
coding," in Proc. Int'l Technical Conference on Circuits/Systems,
Computers and Communications, pp. 12691272, July 1998.

D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and
T. Kasami: "VLSI implementation of a recursive maximum likelihood
decoder for highspeed satellite communication," in Proc. Int'l
Technical Conference on Circuits/Systems, Computers and
Communications, pp. 13831386, July 1998.

B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa: "Lowpower
implementation by a new logic scheme of NMOS 4phase dynamic logic,"
in Proc. Synthesis and System Integration of Mixed Technologies,
pp. 235240, Oct. 1998.

B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa: "Delay and
power simulation for a new logic scheme of NMOS 4phase dynamic
logic," in Proc. European Simulation Symposium, pp.339343,
Oct. 1998.

J. Fan, G. Fujita, M. Furuie, T. Onoye, I. Shirakawa:
"Structual objectoriented video segmentation and representation
algorithm," in Proc. IEEE International Workshop on Intelligent
Signal Processing and Communication Systems, pp. 7882 Nov. 1998.

H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and
I. Shirakawa: "Hybrid VLSI architecture for motion compensation and
texture mapping," in Proc. IEEE International Workshop on
Intelligent Signal Processing and Communication Systems,
pp. 383386, Nov. 1998.

H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and
K. Matsumura: "Matrixvector multiplier module for
natural/synthetic hybrid video coding," in Proc. IEEE Asia Pacific
Conference on Circuits and Systems, pp. 631634, Nov. 1998.

K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano,
T. Honda, T. Otsuki, T. Baba, and T. Meng: "Multimode and
multilevel technologies for FeRAM embedded reconfigurable
hardware," in IEEE Int'l SolidState Circuits Conference (ISSCC)
Diegest of Technical Papers, pp. 106107, Feb. 1999.

G. Fujita, H. Okuhata, M. H. Miki, K. Matsumura, T. Onoye, and
I. Shirakawa: "Lowpower architecture of H.324 codec dedicated to
mobile computing," in Proc. EUROMEDIA, pp. 145149, April 1999.

M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa,
T. Fujiwara, and T. Kasami:
"Recursive maximum likelihood decoder for highspeed satellite
communication," in Proc. International Symposium on
Circuits and Systems, pp. 572575, June 1999.

H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa:
"Hybrid mediaprocessor core for natural and synthetic video
decoding," in Proc. International Symposium on
Circuits and Systems, pp. 275278, June 1999.

B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa:
"Array macro cell architecture for lowpower NMOS 4phase
dynamic logic," in Proc. International Technical Conference on
Circuits/Systems, Computers and Communications, pp. 561564,
July 1999.

M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa:
"Pipelined implementation of JBIG arithmetic coder,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 470473, July 1999.

R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa:
"Embedded zerotree wavelet based algorithm for video
compression," in Proc. IEEE Region 10 Conference,
pp. 13431346, Sept. 1999.

M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa:
"Layout generation for lowpower NMOS 4phase dynamic logic
array," in Proc. IEEE Region 10 Conference,
pp. 872875, Sept. 1999.

M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa:
"Highspeed implementation of JBIG arithmetic coder,"
in Proc. IEEE Region 10 Conference, pp. 12911294,
Sept. 1999.

R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa:
"Architecture of embedded zerotree wavelet based realtime video
coder," in Proc. ASIC/SOC Conference,
pp. 137141, Sept. 1999.

R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa:
"Video coding algorithm based on modified discrete wavelet
transform," in Proc. Nonlinear Theory and Its
Application, pp. 251254, Nov. 1999.

M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa:
"Layout generation of array cell for NMOS 4phase dynamic logic,"
in Proc. Asia and South Pacific Design Automation
Conference, pp. 529532, Jan. 2000.

Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa:
"Chameleon: A dynamically reconfigurable hardwarebased
cryptosystem," in Proc. EUROMEDIA, pp. 9094, May 2000.

D. Murakami, T. Izumi, T. Onoye, and Y. Nakamura:
"A hardware algorithm of dynamic area allocation to circuits
for plastic cell architecture," in Proc. EUROMEDIA,
pp. 8589, May 2000.

R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada,
D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa:
"VLSI implementation of a realtime wavelet video coder,"
in Proc. Custom Integrated Circuits
Conference, pp. 543546, May 2000.

Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa:
"VLSI implementation of dynamically reconfigurable
hardwarebased cryptosystem," in Symposium on VLSI
Circuits Digest of Technical Papers, pp. 204205, June 2000.

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa:
"Low power DSP implementation of 3D sound localization,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 253256, July 2000.

W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa:
"3D acoustic image localization algorithm by embedded DSP,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 264267, July 2000.

R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa:
"Discrete cosine transformer with variablelength basis
vector for MPEG4 video codec,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 811814, July 2000.

S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa:
"VLSI implementation of portable MPEG4 audio decoder,"
in Proc. ASIC/SOC Conference,
pp. 8084, Sept. 2000.

Y. Dong, R. Y. Omaki, T. Onoye, and I. Shirakawa:
"VLSI implementation of a reduced memory bandwidth realtime
EZW video coder,"
in Proc. International Conference on Image Processing,
pp. 126129, Sept. 2000.

Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa:
"A dynamically reconfigurable hardwarebased cipher chip,"
in Proc. Asia and South Pacific Design Automation
Conference, pp. 1112, Jan. 2001.

R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki,
M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa:
"Realtime wavelet video coder based on reduced memory
accessing,"
in Proc. Asia and South Pacific Design Automation
Conference, pp. 1516, Jan. 2001.

Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa:
"A high performance burst mode approach for 128bit block ciphers,"
in Proc. EUROMEDIA, pp. 146150, April 2001.

M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa:
"Twodimensional array layout for low power NMOS 4phase
dynamic logic,"
in Proc. International Conference Electronics Packaging,
pp. 417421, April 2001.

Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa:
"VLSI architecture of dynamically reconfigurable hardwarebased
cipher,"
in Proc. International Symposium on Circuits and Systems,
pp. IV.734IV.737, May 2001.

K. Chikamura, T. Izumi, T. Onoye, and Y. Nakamura:
"IEEE1394 system simulation environment and a eesign of its
link layer controller,"
in Proc. International Symposium on Circuits and Systems,
pp. V.1V.4, May 2001.

H. Tsutsui, K. Hiwada, T. Izumi, T. Onoye, and Y. Nakamura:
"A design of LUTarraybased PLD and a synthesis approach based
on sum of generalized complex terms expression,"
in Proc. International Symposium on Circuits and Systems,
pp. V.203V.206, May 2001.

H. Okada, H.S. Song, G. Fujita, T. Onoye, and I. Shirakawa:
"Error detection based on check marker embedding for MPEG4
video coding,"
in Proc. International Technical Conference on
Circuits/Systems, Computers and Communications, pp. 9699,
July 2001.

H.S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa:
"Error concealment algorithm by motion estimation method for
MPEG4 video decoder," in Proc. International Technical
Conference on Circuits/Systems, Computers and Communications,
pp. 104107, July 2001.

T. Song, G. Fujita, T. Onoye, and I. Shirakawa:
"Low power architecture for H.263 version 2 codec,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 620623, July 2001.

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa:
"DSP implementation of realtime 3D sound localization algorithm,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 11401143, July 2001.

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa:
"Low power DSP implementation of 3D sound localization for
monaural sound source,"
in Proc. World Multiconference on Systemics, Cybernetics and
Informatics, pp. 173177, July 2001.

H. Tsutsui, T. Masuzaki, M. Oyamatsu, T. Izumi, T. Onoye, and
Y. Nakamura:
"Design of JPEG2000 encoder for fully scalable image coding,"
in Proc. World Multiconference on Systemics,
Cybernetics and Informatics, pp. 546551, July 2001.

M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa:
"Twodimensional array layout for NMOS 4phase dynamic logic,"
in Proc. International Conference on Electronics,
Circuits and Systems, pp. 589592, Sept. 2001.

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa:
"DSP implementaion of 3D sound localization algorithm for monaural
sound source,"
in Proc. International Conference on Electronics,
Circuits and Systems, pp. 10611064, Sept. 2001.

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa:
"DSP implementation of low computational 3D sound localization
algorithm,"
in Proc. Workshop on Signal Processing Systems,
Design and Implementation, pp. 109116, Sept. 2001.

Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa:
"VLSI implementation of high performance burst mode for 128bit
block ciphers," in Proc. ASIC/SOC Conference,
pp. W1.1.1W1.1.5, Sept. 2001.

T. Okamoto, K. Sakai, A. Tomita, S. Sugimoto, T. Izumi, T. Onoye,
and Y. Nakamura:
"Cbased design automation environment for
plastic cell architecture,"
in Proc. Workshop on Synthesis and System Integration
of Mixed Technologies, pp. 4549, Oct. 2001.

H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa:
"An architecture level power estimation method for embedded
systems," in Proc. Workshop on Synthesis and System
Integration of Mixed Technologies, pp. 7885, Oct. 2001.

X. Li, T. Fukushima, T. Izumi, T. Onoye, and Y. Nakamura:
"A HW/SW design of an MP3 decoder,"
in Proc. Workshop on Synthesis and System Integration
of Mixed Technologies, pp. 327331, Oct. 2001.

Z. Andales, Y. Mituyama, T. Onoye, and I. Shirakawa:
"System performance evaluation of highspeed burst mode for
128bit block ciphers," in Proc. Workshop on Synthesis
and System Integration of Mixed Technologies, pp. 332339,
Oct. 2001.

M. Kimura, M.H. Miki, T. Onoye, and I. Shirakawa:
"High performance Java execution for embedded systems,"
in Proc. Workshop on Synthesis and System Integration of Mixed
Technologies, pp. 346350, Oct. 2001.

M. Ise, Y. Uchida, T. Onoye, and I. Shirakawa:
"Systemonachip architecture for WCDMA baseband modem LSI,"
in Proc. International Conference on ASIC,
pp. 364369, Oct. 2001.

M.H. Miki, M. Kimura, T. Onoye, and I. Shirakawa:
"High performance Java hardware engine and software kernel for
embedded systems,"
in Proc. International Conference on Very Large Scale
Integration, pp. 365369, Dec. 2001.

M. Kimura, M.H. Miki, T. Onoye, and I. Shirakawa:
"A Java accelerator for high performance embedded systems,"
in Proc. International Conference of Massively Parallel
Computing Systems, pp. 3.2.13.2.6, April 2002.

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "DSP
implementation of realtime 3D sound synthesis algorithm for
monaural sound source," in Proc. EUROMEDIA,
pp. 123127, April 2002.

H. Tsutsui, T. Masuzaki, M. Oyamatsu, T. Izumi, T. Onoye, and
Y. Nakamura: "JPEG2000 fully scalable image encoder by
configurable processor," in Proc. EUROMEDIA,
pp. 168172, April 2002.

Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa:
"Burst mode: A new acceleration mode for 128bit block ciphers,"
in Proc. Custom Integrated Circuits Conference, pp. 151154,
May 2002.

Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye,
I. Shirakawa, and T. Chiba:
"Error correction block based ARQ protocol for wireless digital
video transmission," in Proc. International Symposium on
Circuits and Systems, pp. I.605I.608, May 2002.

H. Yamamoto, K. Chikamura, T. Izumi, T. Onoye, and Y. Nakamura:
"An intelligent IEEE1394 HUB architecture,"
in Proc. International Symposium on Circuits and Systems,
pp. II.249II.252, May 2002.

Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and
I. Arungsrisangchai: "VLSI architecture of burst mode
acceleration for 128bit block ciphers," in
Proc. International Symposium on Circuits and Systems,
pp. II.344II.347, May 2002.

H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa: "Power
Estimation at Architecture Level for Embedded Systems,"
in Proc. International Symposium on Circuits and Systems,
pp. II.476II.479, May 2002.

Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai:
"VLSI architecture of digital matched filter and prime interleaver
for WCDMA," in Proc. International Symposium on
Circuits and Systems, pp. III.269III.272, May 2002.

T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura:
"JPEG2000 adaptive rate control for embedded systems,"
in Proc. International Symposium on Circuits and
Systems, pp. IV.333IV.336, May 2002.

W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa:
"`Outofhead' acoustic field enhancement for stereo
headphones by embedded DSP," in International
Conference on Consumer Electronics Digest of Technical
Papers, pp. 222223, June 2002.

Y. Ohtani, N. Kawahara, T. Onoye, I. Shirakawa, and T. Chiba:
"MAC LSI design for wireless MPEG2 transmission over IEEE802.11b PHY,"
in International Conference on Consumer Electronics Digest of
Technical Papers, pp. 242243, June 2002.

A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa:
"A hardware implementation of Ogg Vorbis audio decoder with embedded
processor,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 9497, July 2002.

S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa:
"Synthesis of 3D sound movement by embedded DSP,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 117120, July 2002.

H. Okada, A.E. Shiitev, H.S. Song, G. Fujita, T. Onoye, and I. Shirakawa:
"Digital watermark based error detection for MPEG4 bitstream error,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 152155, July 2002.

T. Kaya, R. Miyamoto, T. Onoye, and I. Shirakawa: "Embedded system
for video coding with logicenhanced DRAM and configurable
processor,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 216219, July 2002.

H.S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa:
"Hybrid error concealment algorithm for MPEG4 videodecoders,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 611614, July 2002.

T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura:
"Adaptive rate control for JPEG2000 image coding in embedded systems,"
in Proc. International Conference on Image Processing, vol. 3,
pp. 7780, Sept. 2002.

A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa: "VLSI
implementation of Ogg Vorbis decoder for embedded
applications," in Proc. ASIC/SOC Conference,
pp. 2024, Sept. 2002.

H. Yamamoto, K. Chikamura, A. Shigiya, K. Tsujino, T. Izumi, T. Onoye,
and Y. Nakamura: "Systemlevel design of IEEE1394 bus segment
bridge," in Proc. International Symposium on System
Synthesis, pp. 7479, Oct. 2002.

K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa:
"Realtime face object extraction algorithm for video phone,"
in Proc. AsiaPacific Conference on Circuits and Systems,
vol. 1, pp. 3538, Dec. 2002.

Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba,
T. Onoye, and I. Shirakawa: "Implementation of wireless MPEG2
transmission system using IEEE 802.11b PHY,"
in Proc. AsiaPacific Conference on Circuits and Systems,
vol. 1, pp. 3944, Dec. 2002.

H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura,
"High speed JPEG2000 encoder by configurable processor,"
in Proc. AsiaPacific Conference on Circuits and Systems,
vol. 1, pp. 4550, Dec. 2002.

N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and
I. Shirakawa:
"Embedded implementation of acousitic field enhancement for stereo
headphones,"
in Proc. AsiaPacific Conference on Circuits and Systems,
vol. 1, pp. 5054, Dec. 2002.

T. Yuasa, A. Tomita, T. Izumi, T. Onoye, and Y. Nakamura:
"An approach for circuit size reduction by variable reordering for
PCAchip2,"
in Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.217221, April 2003.

T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa:
"VLSI architecture for MPEG4 core profile codec core,"
in Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.365371, April 2003.

Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and
Y. Nakamura:
"Scalable design framework for JPEG2000 encoder architecture,"
in Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.372376, April 2003.

N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and
I. Shirakawa:
"Low cost approach to acoustic field enhancement for stereo
headphones,"
in Proc. EUROMEDIA, pp. 3236, April 2003.

T. Yuasa, Y. Soga, T. Izumi, T. Onoye, and Y. Nakamura:
"An improved communication channel in dynamic reconfigurable device
for multimedia applications,"
in Proc. EUROMEDIA, pp. 152157, April 2003.

S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and
I. Shirakawa:
"Interactive interface of realtime 3D sound movement for embedded
applications,"
in Proc. International Symposium on Circuits and Systems,
pp. 520523, May 2003.

Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and
Y. Nakamura:
"Design framework for JPEG2000 encoding system architecture,"
in Proc. International Symposium on Circuits and Systems,
pp. 740743, May 2003.

T. Izumi, K. Tada, T. Yuasa, T. Onoye, and Y. Nakamura:
"An adaptive load distribution model for selfreconfigurable logic
device,"
in Proc. Northeast Workshop on Circuit and Systems, pp. 1316,
June 2003.

N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa:
"Embedded implementation of acoustic field enhancement for stereo
sound sources,"
in International Conference on Consumer Electronics Digest of
Technical Papers, pp. 256257, June 2003.

A. Kotani, Y. Asai, Y. Nakamura, S. Okada, N. Koyama, K. Yamane,
Y. Okano, Y. Mitsuyama, and T. Onoye:
"Visibility font technology on high resolution color LCD LCFONT.C,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 535538, July 2003.

S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and Isao Shirakawa:
"Low power Ogg Vorbis decoder by embedded processor,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 565568, July 2003.

T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa:
"Feature extraction of headrelated transfer function for 3D sound
movement,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 685688, July 2003.

H.S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa:
"Efficient error recovery scheme for MPEG4 video coding,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp. 13281331, July 2003.

K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa:
"Modified snake: realtime face object extraction for video phone,"
in Proc. IEEE International Conference on Image Processing, pp. 873876, Sept. 2003.

M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa: "Implementation of
WCDMA channel codec by configurable processors,"
in Proc. Sixth Baiona Workshop on Signal Processing in Communications, pp. 205210, Sept. 2003.

K. Tsujino, A. Shigiya, T. Izumi, T. Onoye, Y. Nakamura, and
W. Kobayashi:
"A DSPbased 3D sound synthesis system for moving sound images,"
in Proc. GAMEON Conference, pp. 2325, Nov. 2003.

K. Tsujino, A. Shigiya, W. Kobayashi, T. Izumi, T. Onoye, and
Y. Nakamura:
"An implementation of moving 3D sound synthesis system based on
floating point DSP,"
in Proc. IEEE International Symposium on Signal Processing and
Information Technology,
pp. WA48.1WA48.4, Dec. 2003.

A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa:
"SoC design of Ogg Vorbis decoder using embedded processor,"
in Proc. Computing Frontier Conference, pp. 481487, April 2004.

H. Sugita, Q.M. Vu, T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and
Y. Nakamura:
"JPEG2000 highspeed progressive decoding scheme,"
in Proc. IEEE International Symposium on Circuits and Systems, pp. 873876, May 2004.

T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa:
"Embedded system implementation of scalable and objectbased video
coding,"
in Proc. World Automation Congress, pp. 076.1076.8, June 2004.

Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa:
"Architecture of Turbo decoder for WCDMA by configurable processor,"
in Proc. International Technical Conference on Circuits/Systems,
Computersand Communications,
pp. 7F2P27.17F2P27.4, July 2004.

Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa:
"Embedded architecture of IEEE802.11i cipher algorithms,"
in Proc. IEEE International Symposium on Consumer Electronics, pp. 241246, Sept. 2004.

S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa:
"Cbased hardware design of IMDCT accelerator for Ogg Vorbis decoder,"
in Proc. European Signal Processing Conference, pp. 13611364, Sept. 2004.

H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and
Nakamura:
"Scalable design framework for JPEG2000 system architecture,"
in Proc. AsiaPacific Computer Systems Architecture Conference, pp. 296308, Sept. 2004.

J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura,
"A scalable approach for estimation of focus of expansion,"
in Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pp. 611, Sept. 2004.

N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa:
"VLSI implementation of a 3D sound movement system,"
in Proc. Workshop on Synthesis And System Integration of Mixed Information technologies, pp.121125, Oct. 2004.

N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa:
"VLSI implementation of 3D sound image movement for embedded systems,"
in Proc. IEEE Region 10 Conference, pp. 2124, Nov. 2004.

K. Tsujino, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura:
"Realtime filter redesign for interactive 3D sound systems,"
in Proc. IEEE Region 10 Conference, pp. 124127, Nov. 2004.

R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and
Y. Nakamura:
"Video quality enhancement for Motion JPEG2000 encoding based on the
human visual system,"
in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 11611164, Dec. 2004.

T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa:
"Embedded 3D sound movement system based on feature extraction of
headrelated transfer function,"
International Conference on Consumer Electronics Digest of Technical Papers, pp. 7.17.2, Jan. 2005.

R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye,
and Y. Nakamura:
"High quality motion JPEG2000 coding scheme based on the human visual
system,"
in Proc. IEEE Int’l Symp. Circuits and Systems, pp. 20962099, May 2005.

T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and
I. Arungsrisangchai:
"3D sound movement system for embedded applications,"
in Proc. IEEE Int’l Symp. Circuits and Systems, pp. 53455348, May 2005.

Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa:
"An approach for areaefficient coarsegrained reconfigurable
architecture dedicated to media processing,"
in Proc. International Technical Conference of Circuits/Systems,
Computers and Communications,
pp. 131132, July 2005.

H. V. Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa:
"Fast human object extraction method based on color space segmentation
for mobile systems,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communications, pp.10151016, July 2005.

Y. Ogasahara, M. Hashimoto, and T. Onoye:
"Measurement and analysis of delay variation due to inductive
coupling,"
in Proc. IEEE Custom Integrated Circuits Conference, pp.305308, 2005.

Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa:
"A lowcomplexity FEC assignment scheme for Motion JPEG2000 over
wireless network,"
in International Conference on Consumer Electronics Digest of Technical Papers, pp. 391392, Jan. 2006.

K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye:
"A gate delay model focusing on current fluctuation over widerange of
process and environmental variability,"
in Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 5964, Feb. 2006.

Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa:
"Domainspecific reconfigurable architecture for media processing,"
in Proc. Workshop on Synthesis and System Integration of Mixed
Technologies (SASIMI 2006), pp. 322327, April 2006.

A. Kotani, Y. Tanemura, Y. Mitsuyama, Y. Asai, Y. Nakamura, and
T. Onoye:
"Contourbased gravity center evaluation of characters,"
in Proc. EUROMEDIA, pp. 1520, April 2006.

K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura:
"Automated design of digital filters for 3D sound localization in
embedded applications,"
in Proc. International Conf. Audio, Speech, and Signal Processing
(ICASSP2006), pp. V.349V.352, May 2006.

H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and
Y. Nakamura:
"Efficient memory architecture for JPEG2000 entropy codec,"
in Proc. International Symposium on Circuits and Systems,
pp. 28812884, May 2006.

A. Kosaka and T. Onoye:
"Pipeline processing of continuous speech recognition algorithm for
embedded system implementation,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communication, vol. II, pp. 373376, July 2006.

F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura:
"A JPEG coding scheme for high fidelity images by halftoning less
signification extra bits,"
in Proc. International Technical Conference on Circuits/Systems,
Computers and Communication, vol. III, pp. 97100, July 2006.

Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye:
"Measurement results of delay degradation due to power supply noise
well correlated with fullchip simulation,"
in Proc. Custom Integrated Circuits Conference, pp. 861864,
Sept. 2006.

Y. Ogasahara, M. Hashimoto, and T. Onoye:
"Measurement of inductive coupling effect on timing in 90nm global
interconnects,"
in Proc. Custom Integrated Circuits Conference, pp. 721724,
Sept. 2006.

Y. Ogasahara, M. Hashimoto, and T. Onoye:
"Quantitative prediction of onchip capacitive and inductive crosstalk
noise and discussion on wire crosssectional area toward inductive
crosstalk free interconnects,"
in Proc. International Conference on Computer Design,
pp. 7075, Oct. 2006.

J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura:
"Probabilistic pedestrian tracking based on a skeleton model,"
in Proc. International Conference on Image Processing,
pp. 28252828, Oct. 2006.

K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye: "A gate delay
model focusing on current fluctuation over widerange of process and
environmental variability," in Proc. International Conference on
ComputerAided Design, pp. 4753, Nov. 2006.

R. Hashimoto, K. Katou, G. Fujita, and T. Onoye:
"VLSI architecture of H.264 block size decision based on
ratedistortion optimization," in Proc. International Symposium on
Intelligent Signal Processing and Communication Systems, pp. 618621,
Dec. 2006.

K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi: “An
energyefficient architecture of wireless home network based on MAC
broadcast and transmission power control,” in International
Conference on Consumer Electronics Digest of Technical Papers,
P120, Jan. 2007.

K. Shinkai, M. Hashimoto, and T. Onoye: "Future prediction of
selfheating in short intrablock wires," in Proc. International
Symposium on Quality Electronic Design, pp. 660665, March 2007.

M.N.B. Mohd Nor, T. Matsumura, and T. Onoye: "Direction of arrival
estimation Improvement of speech on a twomicrophone array," in
Proc. IASTED International Conf. Signal and Image
Processing, 576.115, August 2007.

Y. Ogasahara, M. Hashimoto, and T. Onoye: "Dynamic supply noise
measurement with all digital gated oscillator for evaluating
decoupling capacitance effect," in Proc. IEEE Custom
Integrated Circuits Conference, pp. 783786, September 2007.

K. Takahashi, Y. Nozato, H. Okuhata, and T. Onoye: "VLSI architecture
for realtime retinex video image enhancement," in
Proc. Workshop on Synthesis and System Integration of Mixed
Technologies (SASIMI 2007), pp. 8186, October 2007.

K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "A
study on bodybiasing layout style focusing on area efficiency
and speed controllability," in Proc. Workshop on
Synthesis and System Integration of Mixed Technologies (SASIMI
2007), pp. 233237, October 2007.

R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye:
"Implementation of object attention based on multiagent
attractor selection," in Proc. International Workshop
on Smart InfoMedia Systems in Bangkok, pp. 2333, November
2007.

R. Hashimoto, K. Kato, G. Fujita, and T. Onoye: "VLSI
architecture of H.264 RDObased block size decision for 1080
HD," in Proc. Picture Coding Symposium, ThPM4.9, November 2007.

Y. Manabe, J. Hara, and T. Onoye: "JPMbased
differential image storage scheme for image revision management
system," in Proc. IIEEJ Image Electronics and Visual Computing
Workshop 2007, 2C2, November 2007.

J. Hara, B.R. Mohsen, and T. Onoye: "Structure
representation and reference method for JPEG 2000 family
formats," in Proc. IIEEJ Image Electronics and Visual Computing
Workshop 2007, 2C3, November 2007.

Y. Ogasahara, M. Hashimoto, and T. Onoye: "Dynamic supply
noise measurement circuit composed of standard cells suitable
for insite SoC power integrity verification," in Proc. IEEE/ACM
Asia and South Pacific Design Automation Conference,
pp. 107108, January 2008.

S. Abe, M. Hashimoto, and T. Onoye: "Clock skew
evaluation considering manufacturing variability in meshstyle
clock distribution," in Proc. International Sympos.
Quality Electronic Design (ISQED), pp. 520525, March 2008.

H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa:
"Video image enhancement scheme for high resolution consumer
devices," in Proc. International Symposium on
Communications, Control, and Signal Processing, pp. 639644,
March 2008.

K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye:
"Experimental study on bodybiasing layout style  Negligible area
overhead enables sufficient speed controllability ," in Proc. Great
Lakes Symposium on VLSI, pp. 387390, May 2008.

H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Correlation
verification between transistor variability model with body biasing
and ring oscillation frequency in 90nm subthreshold circuits," in
Proc. International Symposium on Low Power Electronics and Design,
pp. 38, August 2008.

M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi: "A 3D
sound localization method for multiple sound sources based on Fuzzy
clustering," in Proc. International Workshop on Smart InfoMedia
Systems in Bangkok, pp. 133138, December 2008.

H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Tradeoff
analysis between timing error rate and power dissipation for adaptive
speed control with timing error prediction," in Proc. Asia and South
Pacific Design Automation Conference, pp. 266271, January 2009.

M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi: "An
embedded sound localization system for multiple sources by Fuzzy
clustering with spatial constraints," in Proc. International Workshop
on Nonlinear Circuits and Signal Processing, pp. 257260, March
2009.

R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi,
S. Miyamoto, and S. Sampei: "Implementation of OFDM baseband
transceiver with dynamic spectrum access for cognitive radio systems,"
in Proc. International Symposium on Communication and Information
Technology, pp. 658663, September 2009.

H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Adaptive
performance compensation with insitu timing error prediction for
subthreshold circuits," in Proc. IEEE Custom Integrated Circuits
Conference, pp. 215218, September 2009.

H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Adaptive
performance control with embedded timing error predictive sensors for
subthreshold circuits," in Proc. Asia and South Pacific Design
Automation Conference, pp. 361362, January 2010.

S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye: "Clock skew reduction
by selfcompensating manufacturing variability with onchip sensors,"
in Proc. International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems, pp. 8994, March 2010.

R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye: "Measurement
circuits for acquiring SET pulsewidth distribution with
subFO1inverterdelay resolution," in Proc. International Symposium
on Quality Electronic Design, pp. 839844, March 2010.

H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye: "Comparative
study on delay degrading estimation due to NBTI with
circuit/instance/transistorlevel stress probability consideration,"
in Proc. International Symposium on Quality Electronic Design,
pp. 646651, March 2010.

Y. Kawamura, Y. Manabe, T. Onoye, K. Ohara, H. Okada, and I. Keshi:
"Implementation of simultaneous video decoding on multicore
processor," in Proc. International Symposium on Communications,
Control and Signal Processing, pp. 14, March 2010.

D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye: "A 16bit RISC
processor with 4.18pJ/cycle at 0.5V operation," in Proc. IEEE COOL
Chips, p. 190, April 2010.

Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye: "Measurement of
onchip I/O power supply noise and correlation verification between
noise magnitude and delay increase due to SSO," in Proc. IEEE Wrokshop
on Signal Propagation on Interconnects, pp. 1920, May 2010.

S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye: "Clock skew reduction
by selfcompensating manufacturing variability with onchip sensors,"
in Proc. Great Lakes Symposium on VLSI, pp. 197202, May 2010.

L. M. Handaya, M. Okada, T. Onoye, and W. Kobayashi: "Improvement of
frontal localization with complement of multiple delayed sounds," in
Proc. International Workshop on Information Communication Technology,
pp. S1.5.1S1.5.4, August 2010.

Y. Takai, M. Hashimoto, and T. Onoye: "Evaluation of power gating
structures focusing on power supply noise with measurement and
simulation," in Proc. Electrical Performance of Electronic Packaging
and Systems, pp. 213216, October 2010.

M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi,
S. Miyamoto, and S. Sampei: "VLSI design of OFDM baseband transceiver
with dynamic spectrum access," in Proc. International Symposium on
Intelligent Signal Processing and Communication Systems, pp. 329332,
December 2010.

T. Amaki, M. Hashimoto, and T. Onoye: "Jitter amplifier for
oscillatorbased true random number generator," in Proc. Asia and
South Pacific Design Automation Conference, pp. 8182, January
2011.

T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "A design
procedure for oscillatorbased hardware random number generator with
stochastic behavior modeling," in Proc. International Workshop on
Information Security Applications, pp. 107121, January 2011.

T. Maeno, H. Tsutsui, and T. Onoye: "Hardware implementation of
realtime motion adaptive deinterlacing based on inpainting," in
Proc. International Conference on Embedded Systems and Intelligent
Technology, pp. 159164, February 2011.
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