Selected Publications of Takao ONOYE


Journal Publications

  1. T. Onoye, A. Yamada, I. Arungsrisangchai, M. Tanaka and I. Shirakawa: "An automatic layout generator for bipolar analog modules," IEICE Trans. Fundamentals, vol. E75-A, no. 10, pp. 1306-1314, Oct. 1992.
  2. T. Onoye, T. Masaki, I. Shirakawa, H. Hirata, K. Kimura, S. Asahara, and T. Sagishima: "High-level synthesis of a multithreaded processor for image generation," IEICE Trans. Fundamentals, vol. E78-A, no. 3, pp. 322-330, March 1995.
  3. T. Masaki, Y. Morimoto, T. Onoye, and I. Shirakawa: "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding," IEEE Trans. Circuits and Systems for Video Technology, vol. 5, no. 5, pp. 387-395, Oct. 1995.
  4. T. Onoye, T. Masaki, Y. Morimoto, Y. Sato, I. Shirakawa, and K. Matsumura: "Single chip implementation of MPEG2 decoder for HDTV level pictures," IEICE Trans. Fundamentals, vol. E79-A, no. 3, pp. 330-338, March 1996.
  5. T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai: "Single chip implementation of motion estimator dedicated to MPEG2 MP@HL," IEICE Trans. Fundamentals, vol. E79-A, no. 8, pp. 1210-1216, Aug. 1996.
  6. T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami: "Voice and telephony over ATM for multimedia network using shared VCI cell," Journal of Circuits, Systems and Computers, vol. 7, no. 2, pp. 93-110, April 1997.
  7. 吉田幸弘,宋宝玉,奥畑宏之,尾上孝雄,白川功: "組込み用プロセッサの低消費電力化に関する一手法," 電子情報通信学会論文誌}, vol. J80-A, no. 5, pp. 765-771, May 1997 (in Japanese).
  8. K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa: "Single chip implementation of encoder-decoder for low bitrate visual communication," Journal of Circuits, Systems and Computers, vol. 7, no. 5, pp. 441-457, Oct. 1997.
  9. T. Masaki, Y. Nakatani, T. Onoye, N. Yamai, and K. Murakami: "Voice communication on multimedia ATM network using shared VCI cell," IEICE Trans. Communications, vol. E81-B, no. 2, pp. 340-346, Feb. 1998.
  10. 木村浩三,奥畑宏之,尾上孝雄,白川功,清原督三,鷺島敬之: "マルチスレッドプロセッサのデータキャッシュ制御方式," 映像情報メディア学会誌, vol. 52, no. 5, pp. 742-749, May 1998 (in Japanese).
  11. G. Fujita, T. Onoye, and I. Shirakawa: "A VLSI architecture for motion estimation core dedicated to H.263 video coding," IEICE Trans. Electronics, vol. E81-C, no. 5, pp. 702-707, May 1998.
  12. H. Okuhata, M.H. Miki, T. Onoye, and I. Shirakawa: "A low-power DSP architecture for low bitrate speech codec," IEICE Trans. Fundamentals, vol. E81-A, no. 8, pp. 1616-1621, Aug. 1998.
  13. M.H. Miki, 藤田玄,尾上孝雄,白川功: "携帯端末向け低電力H.263 コーデック・コアのVLSI化設計," 電子情報通信学会論文誌, vol. J81-A, no. 10, pp. 1352-1361, Oct. 1998 (in Japanese).
  14. H. Fujishima, Y. Takemoto, T. Onoye, and I. Shirakawa: "An architecture of matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics," IEEE Trans. Circuits and Systems for Video Technology, vol. 9, no. 2, pp. 306-314, March 1999.
  15. B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa: "Low-power scheme of NMOS 4-phase dynamic logic," IEICE Trans. Electronics, vol. E82-C, no. 9, pp. 1772-1776, Sept. 1999.
  16. J. Fan, G. Fujita, M. Furuie, T. Onoye, I. Shirakawa, and L. Wu: "Automatic moving object extraction toward compact video representation," Optical Engineering, vol. 39, no. 2, pp. 438-452, Feb. 2000.
  17. M. Hatanaka, T. Masaki, T. Onoye, and K. Murakami: "VLSI architecture of switching control for AAL type2 switch," IEICE Trans. Fundamentals, vol. E83-A, no. 3, pp. 435-441, March 2000.
  18. B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa: "Low-power VLSI implementation by NMOS 4-phase dynamic logic," Trans. IPSJ, vol. 41, no. 4, pp. 899-907, April 2000.
  19. J. Fan, J. Yu, G. Fujita, T. Onoye, L. Wu, and I. Shirakawa: "Spatiotemporal segmentation for compact video representation," Signal Processing: Image Communication, vol. 16, no. 6, pp. 553-566, Feb. 2001.
  20. Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa: "A novel dynamically reconfigurable hardware-based cipher," Trans. IPSJ, vol. 42, no. 4, pp. 958-966, April 2001.
  21. W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa: "3D acoustic image localization algorithm by embedded DSP," IEICE Trans. Fundamentals, vol. E84-A, no. 6, pp. 1423-1430, June 2001.
  22. H. Tsutsui, A. Tomita, S. Sugimoto, K. Sakai, T. Izumi, T. Onoye, and Y. Nakamura: "LUT-array-based PLD and synthesis approach based on sum of generalized complex terms expression," IEICE Trans. Fundamentals, vol. E84-A, no. 11, pp. 2681-2689, Nov. 2001.
  23. R.Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa: "An embedded zerotree wavelet video coding algorithm with reduced memory bandwidth requirements," IEICE Trans. Fundamentals, vol. E85-A, no. 3, pp. 703-713, March 2002.
  24. 宋天, 藤田玄, 尾上孝雄, 白川功: "携帯端末用低消費電力 H.263 Version 2 コーデックコアのVLSI化設計," 情報処理学会論文誌, vol. 43, no. 4, pp. 1161-1170, May 2002 (in Japanese).
  25. H. Okada, A.E. Shiitev, H.S. Song, G. Fujita, T. Onoye, and I. Shirakawa: "Error detection by digital watermarking for MPEG-4 video coding," IEICE Trans. Fundamentals, vol. E85-A, no. 6, pp. 1281-1288, June 2002.
  26. 岡田浩行, 宋学燮, 藤田玄, 尾上孝雄, 白川功: "電子透かしのMPEG-4ビットストリームエラー検出への応用," 画像電子学会誌,, vol. 31, no. 5, pp. 900-908, Sept. 2002 (in Japanese).
  27. Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, I. Shirakawa: "Wireless digital video transmission system using IEEE802.11b PHY with error correctio block based ARQ protocol," IEICE Trans. Communications, vol. E85-B, no. 10, pp. 2032-2043, Oct. 2002.
  28. H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa: "Performance estimation at architecture level for embedded systems," IEICE Trans. Fundamentals, vol. E85-A, no. 12, pp. 2636-2644, Dec. 2002.
  29. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "Single DSP implementation of realtime 3D sound synthesis algorithm," Journal of Circuits, Systems and Computers, vol. 12, no. 1, pp. 55-73, Feb. 2003.
  30. K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa: "Object sharing scheme for heterogenous environment," IEICE Trans. Fundamentals, vol. E86-A, no. 4, pp. 813-821, April 2003.
  31. T. Okamoto, T. Yuasa, T. Izumi, T. Onoye, and Y. Nakamura: "Design tools and trial design for PCA-Chip2," IEICE Trans. Information and Systems, vol. E86-D, no. 5, pp. 868-871, May 2003.
  32. N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa: " Embedded implementation of acoustic field enhancement for stereo sound sources," IEEE Trans. Consumer Electronics, vol. 49, no. 3, pp. 737-741, Aug. 2003.
  33. 宋学燮, 岡田浩行, 藤田玄, 尾上孝雄, 白川功: "MPEG-4動画像符号化向けハイブリッドエラー隠蔽方式," 画像電子学会誌, vol. 32, no. 5, pp. 609-620, Sept. 2003.
  34. 小谷章夫, 小山至幸, 密山幸男, 尾上孝雄: "低解像度表示デバイス向けフォントLCFONTの重心および可読性の評価," 画像電子学会誌, vol. 32, no. 5, pp. 621-628, Sept. 2003.
  35. M. Kimura, M.H. Miki, T. Onoye, and I. Shirakawa: "Implementation of Java accelerator for high performance embedded systems," IEICE Trans. Fundamentals, vol. E86-A, no. 12, pp. 3079-3088, Dec. 2003.
  36. 岡田勉, 内田翼, 尾上孝雄, 白川功: "次世代GNSS受信機用信号処理機構とそのVLSI化設計," 電子情報通信学会論文誌, vol. J86-A, no. 12, pp. 1417-1425, Dec. 2003.
  37. T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa: "Embedded 3D sound movement system based on feature extraction of head-related transfer function," IEEE Transactions on Consumer Electronics, vol. 51, no. 1, pp. 262-267, Feb. 2005.
  38. Y. Mituyama, M. Kimura, T. Onoye, I. Shirakawa: "Architecture of IEEE802.11i cipher algorithms for embedded systems," IEICE Trans. Fundamentals, vol. E88-A, no. 4, pp. 899-906, April 2005.
  39. K. Tsujino, K. Furuya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura: "Design of realtime 3-D sound processing system," IEICE Trans. Information and Systems, vol. E88-D, no. 5, pp.954-962, May 2005.
  40. A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa: "Desing of Ogg Vorbis decoder system for embedded platform," IEICE Trans. Fundamentals, vol. E88-A, no. 8, pp. 2124-2130, Aug. 2005.
  41. 藤田玄, 尾上孝雄, 白川功: "MPEG-4向け高精度動き検出コアのVLSI化設計," 電子情報通信学会論文誌, vol. J88-A, no. 11, pp. 1282-1291, Nov. 2005.
  42. Z. Guo, Y. Nishikawa, R.Y. Omaki, T. Onoye, and I. Shirakawa: "A low-complexity FEC assignment scheme for Motion JPEG2000 over wireless network," IEEE Trans. Consumer Electronics, vol. 52, no. 1, pp. 81-86, Feb. 2006.
  43. M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa: "W-CDMA channel codec by configurable processors," Journal of Intelligent Automation and Soft Computing, vol.13, no. 3, pp. 318-330, March 2006.
  44. H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura: "Design framework for JPEG2000 system architecture," Journal of Intelligent Automation and Soft Computing, vol. 13, no. 3, pp. 331-343, March 2006.
  45. G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa: "Real-time human object extraction method for mobile systems based on color space segmentation," IEICE Trans. Fundamentals, vol. E89-A, no. 4, pp. 941-949, April 2006.
  46. 小谷章夫, 種村嘉高, 密山幸男, 朝井宣実, 中村安久, 尾上孝雄: "ポテンシャルエネルギーを用いた文字重心位置取得手法," 画像電子学会誌, vol. 35, no. 4, pp.296-305, Sept. 2006.
  47. K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi: "An energy-efficient architecture of wireless home network based on MAC broadcast and transmission power control," IEEE Trans. Consumer Electronics, vol. 53, no. 1, pp. 124-130, Feb. 2007.
  48. K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura: "Efficient 3-D sound movement with time-varying IIR filters," IEICE Trans. Fundamentals, vol. E90-A, no. 3, pp. 618-624, March 2007.
  49. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Quantitative prediction of on-chip capacitive and inductive crosstalk noise and tradeoff between wire cross sectional area and inductive crosstalk effect," IEICE Trans. Fundamentals, vol. E90-A, no. 4, pp. 724-731, April 2007.
  50. K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura: "Automatic filter design for 3-D sound movement in embedded applications," Acoustical Science and Technology, vol. 28, no. 4, pp. 219-229, July 2007.
  51. M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa: "Design and implementation of home network protocol for appliance control based on IEEE 802.15.4," International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.
  52. Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye: "Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement," IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, no. 10, pp. 868-872,October 2007.
  53. N. Iwanaga, T. Matsumura, A. Yoshida, W. Kobayashi, and T. Onoye: "Embedded system implementation of sound localization in proximal region," IEICE Trans. Fundamentals vol. E91-A, no. 3, pp. 763-771,March 2008.
  54. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Measurement and analysis of inductive coupling noise in 90nm global interconnects," IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718-728,March 2008.
  55. R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye: "Implementation of multi-agent object attention system based on biologically inspired attractor selection," IEICE Trans. Fundamentals, vol. E91-A, no. 10, October 2008.
  56. Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa: "Area-efficient reconfigurable architecture for media processing," IEICE Trans. Fundamentals, vol. E91-A, no. 12, pp. 3651-3662, December 2008.
  57. S. Abe, M. Hashimoto, and T. Onoye: "Clock skew evaluation considering manufacturing variability in mesh-style clock distribution," IEICE Trans. Fundamentals, vol. E91-A, no. 12, pp. 3481-3487, December 2008.
  58. T. Masuzaki, H. Tsutsui, Q.M. Vu, T. Onoye, and Y. Nakamura: "JPEG2000 high-speed SNR progressive decoding scheme," International Journal of Computer Science and Network Security, vol. 9, no. 1, pp. 62-68, January 2009.
  59. K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "An experimental study on body-biasing layout style focusing on area efficiency and speed controllability," IEICE Trans. Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.
  60. 増崎隆彦, 筒井弘, 尾上孝雄, 水野雄介, 佐々木元, 中村行宏: "シングルタイ ル JPEG2000 コーデックのシステム構成," 画像電子学会誌, vol. 38, no. 3, pp. 296-304, May 2009.
  61. Y. Ogasahara, M. Hashimoto, T. Onoye: "All digital ring-oscillator based macro for sensing dynamic supply noise waveform," IEEE Journal of Solid-State Circuits, vol. 44, no. 6, pp. 1745-1755, June 2009.
  62. H. Sugano, T. Masuzaki, H. Tsutsui, T. Onoye, H. Ochi, and Y. Nakamura, "Efficient memory organization framework for JPEG2000 entropy codec," IEICE Trans. Fundamentals, vol. E92-A, no. 8, pp. 1970-1977, August 2009.
  63. 畠中理英, 達可敏充, 渡邊賢治, 尾上孝雄: "透過減衰を考慮した無線ホーム ネットワーク向け位置推定," 情報処理学会論文誌, vol. 50, no. 8, pp. 1835-1844, August 2009.
  64. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction," IEICE Trans. Fundamentals, vol. E92-A, no. 12, pp. 3094-3102, December 2009.
  65. K. Shinkai, M. Hashimoto, and T. Onoye: "Prediction of self-heating in short intra-block wires," IEICE Trans. Fundamentals, vol. E93-A, no. 3, pp. 583-594, March 2010.
  66. 渡邊賢治, 達可敏充, 畠中理英, 尾上孝雄: "屋内位置推定システムのための間 取り推定手法," Journal of Signal Processing, vol. 14, no. 3, pp. 231-242, May 2010.
  67. 密山幸男, 高橋一真, 今井林太郎, 橋本昌宜, 尾上孝雄, 白川功: "メディア処 理向け再構成可能アーキテクチャでの動画像復号処理の実現," 電子情報通信学 会論文誌, vol. J93-A, no. 6, pp. 397-413, June 2010.
  68. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Transistor variability modeling and its validation with ring-oscillation frequencies for body-biased subthreshold circuits," IEEE Transactions on VLSI Systems, vol. 18, no. 7, pp. 1118-1129, July 2010.
  69. 大原一人, 芥子育雄, 尾上孝雄: "映像コンテンツ同時閲覧のための負荷適応デ コーダ制御手法," 画像電子学会誌, vol. 39, no. 6, pp. 1095-1103, November 2010.
  70. M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi: "3D sound rendering for multiple sound sources based on Fuzzy clustering," IEICE Trans. Fundamentals, vol. E93-A, no. 11, pp. 2163-2172, November 2010.
  71. R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye: "Measurement circuits for acquiring SET pulse width distribution with sub-FO1-inverter-delay resolution," IEICE Trans. Fundamentals, vol. E93-A, no. 12, pp. 2417-2423, December 2010.

International Conferences

  1. T. Onoye, A. Yamada, I. Arungsrisangchai, M. Tanaka and I. Shirakawa: "An automatic layout generator for bipolar analog modules," in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 2264-2267, May 1992.
  2. T. Onoye, T. Masaki, H. Hirata, K. Kimura, S. Asahara, T. Sagishima, I. Shirakawa, S. Tsukiyama, and S. Shinoda: "High-level synthesis of multithreaded processor based image generator," in Proc. IEEE Int'l Symposium on Industrial Electronics, pp. 47-52, May 1994.
  3. K. Kimura, H. Hirata, T. Kiyohara, S. Asahara, T. Sagishima, T. Onoye, and I. Shirakawa: "Evaluation method of microarchitecture for multithreaded processor," in Proc. IEEE Int'l Symposium on Industrial Electronics, pp. 53-58, May 1994.
  4. T. Sagishima, K. Kimura, H. Hirata, T. Kiyohara, S. Asahara, T. Onoye, and I. Shirakawa: "Multithreaded processor for image generation," in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 4.231-4.234, May 1994.
  5. T. Onoye, T. Masaki, H. Hirata, K. Kimura, S. Asahara, T. Sagishima, I. Shirakawa, S. Tsukiyama, and S. Shinoda: "High-level synthesis of a multithreaded processor for image generation: design and simulation" in Proc. European Simulation Multiconference, pp. 948-953, June 1994.
  6. T. Onoye, T. Masaki, S. Asahara, T. Sagishima, I. Shirakawa, S. Tsukiyama, and S. Shinoda: "Design of multithreaded processor dedicated to image generation: High-level synthesis" in Proc. Joint Technical Conference on Circuits/Systems, Computers, Communication, pp. 689-694, July 1994.
  7. T. Onoye, Y. Morimoto, T. Masaki, and I. Shirakawa: "Design of inverse DCT unit and motion compensator for MPEG2 HDTV decoding," in Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 608-613, Dec. 1994.
  8. T. Masaki, Y. Morimoto, T. Onoye, and I. Shirakawa:  "Specific functional macrocells for MPEG2 single-chip HDTV decoder," in Proc. Joint Technical Conference on Circuits/Systems, Computers, Communication, pp. 499-502, July 1995.
  9. T. Masaki, Y. Morimoto, Y. Sato, T. Onoye, and I. Shirakawa: "Single-chip VLSI decoder for MPEG2 MP@HL," in Proc. Synthesis and System Integration of Mixed Technologies, pp. 211-218, Aug. 1995.
  10. T. Masaki, Y. Morimoto, Y. Sato, T. Onoye, and I. Shirakawa: "Single-chip implementation of MPEG2 decoder dedicated to MP@HL," in Proc. Int'l Conference on VLSI and CAD, pp. 25-28, Oct. 1995.
  11. T. Onoye, M. Takatsu, G. Fujita, I. Shirakawa, and K. Matsumura: "A VLSI implementation of MPEG2 motion estimation algorithm based on macroblock clustering," in Proc. Int'l Conference on VLSI and CAD, pp. 33-36, Oct. 1995.
  12. T. Onoye, T. Masaki, Y. Morimoto, Y. Sato, and I. Shirakawa: "HDTV level MPEG2 video decoder VLSI," in Proc. IEEE TENCON '95 on Microelectronics and VLSI, pp. 468-471, Nov. 1995.
  13. T. Onoye, G. Fujita, M. Takatsu, and I. Shirakawa: "Implementation of MPEG2 MP@HL motion estimator," in Proc. Int'l Conference on Neural Networks and Signal Processing, pp. 1590-1593, Dec. 1995.
  14. T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama: "VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL," in Proc. IEEE Custom Integrated Circuits Conference, pp. 351-354, May 1996.
  15. T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama: "A VLSI architecture of MPEG2 MP@HL motion estimator," in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 664-667, May 1996.
  16. G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa: "Single chip MPEG2 MP@ML motion estimator," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 286-289, July 1996.
  17. K. Miyanohana, G. Fujita, T. Onoye, I. Shirakawa, and N. Yamai: "VLSI architecture for very low bitrate video encoder core," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 294-297, July 1996.
  18. T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura: "A single chip motion estimator dedicated to MPEG2 MP@HL," in Proc. European Signal Processing Conference, pp. 1479-1482, Sept. 1996.
  19. T. Komura, M. Oka, T. Fujiwara, T. Onoye, T. Kasami, and S. Lin: "VLSI architecture of a recursive maximum likelihood decoding algorithm for a (64,35) subcode of the (64,42) Reed-Muller code," in Proc. IEEE Int'l Symp. Information Theory and Its Applications, pp. 709-712, Sept. 1996.
  20. Y. Yoshida B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa: "Low-power consumption architecture for embedded processor," in Proc. 2nd International Conference on ASIC, pp. 77-80, Oct. 1996.
  21. K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa: "Implementation of very low bitrate video encoder core," in Proc. 2nd International Conference on ASIC, pp. 131-134, Oct. 1996.
  22. K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa: "VLSI implementation of edge detector and vector quantizer for very low bitrate video encoding," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 480-483, Nov. 1996.
  23. G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura: "Implementation of half-pel precision motion estimator for MPEG2 MP@HL," in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pp. 949-954, Nov. 1996.
  24. T. Onoye and I. Shirakawa: "VLSI architecture for MPEG2 MP@HL codec," in Proc. Int'l Workshop on Logic and Architecture Synthesis, pp. 251-258, Dec. 1996.
  25. K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa: "VLSI implementation of single chip encoder/decoder for low bitrate visual communication," in Proc. IEEE Custom Integrated Circuits Conference, pp. 229-232, May 1997.
  26. G. Fujita, T. Onoye, and I. Shirakawa: "A new motion estimation core dedicated to H.263 video coding," in Proc. IEEE International Symposium on Circuits and Systems, pp. 1161-1164, June 1997.
  27. T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami: "Multimedia ATM network using shared VCI cell and VLSI implementation of rerouting node," in Proc. IEEE International Symposium on Circuits and Systems, pp. 2793-2796, June 1997.
  28. T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami: "Fellow cell switching for voice communication on multimedia ATM network and its VLSI impelementation," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 1219-1222, July 1997.
  29. H. Fujishima, Y. Takemoto, T. Onoye, and I. Shirakawa: "Media-processor architecture unified for video coding and 3D graphics," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 1223-1226, July 1997.
  30. M. H. Miki, G. Fujita, T. Onoye, S. Tsukiyama, and I. Shirakawa: "Low-power H.263 video codec dedicated to mobile computing," in Proc. ACM/IEEE Int'l Symp. Low Power Electronics Design, pp. 76-79, Aug. 1997.
  31. Y. Yoshida, B.Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa: "An object code compression approach to embedded processors," in Proc. ACM/IEEE Int'l Symp. Low Power Electronics and Design, pp. 265-268, Aug. 1997.
  32. M.H. Miki, G. Fujita, T. Kobayashi, T. Onoye, and I. Shirakawa: "A low-power H.263 video codec core dedicated to mobile computing," in Proc. IFIP Int'l Conf. Very Large Scale Integration, pp. 3-14, Aug. 1997.
  33. H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi: "A unified media-processor architecture for video coding and computer graphics," in Proc. Int'l Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional Imaging, pp. 253-256, Sept. 1997.
  34. Y. Yoshida, T. Onoye, I. Shirakawa, and N. Kubo: "Simulation in low power embedded processor design," in Proc. European Simulation Symposium, pp. 557-561, Oct. 1997.
  35. T. Onoye, G. Fujita, H. Okuhata, M.H. Miki, and I. Shirakawa: "Low-power implementation of H.324 audiovisual codec dedicated to mobile computing," in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 589-594, Feb. 1998.
  36. G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa: "Implementation of H.324 audiovisual codec for mobile computing," in Proc. IEEE Custom Integrated Circuits Conference, pp. 193-196, May 1998.
  37. H. Okuhata, M.H. Miki, T. Onoye, and I. Shirakawa: "A low power DSP core architecture for low bitrate speech codec," in Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal Processing, pp. 3121-3124, May 1998.
  38. Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and I. Shirakawa: "VLSI implementation of function module for texture mapping and motion compensation," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 179-182, July 1998.
  39. R.Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa: "Implementation of DWT and EZW cores for a bitrate-scalable video coder," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 221-224, July 1998.
  40. H. Fujishima, Y. Takemoto, T. Onoye, and I. Shirakawa: "Matrix-vector multiplier for natural/synthetic hybrid video coding," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 1269-1272, July 1998.
  41. D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami: "VLSI implementation of a recursive maximum likelihood decoder for high-speed satellite communication," in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 1383-1386, July 1998.
  42. B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa: "Low-power implementation by a new logic scheme of NMOS 4-phase dynamic logic," in Proc. Synthesis and System Integration of Mixed Technologies, pp. 235-240, Oct. 1998.
  43. B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa: "Delay and power simulation for a new logic scheme of NMOS 4-phase dynamic logic," in Proc. European Simulation Symposium, pp.339-343, Oct. 1998.
  44. J. Fan, G. Fujita, M. Furuie, T. Onoye, I. Shirakawa: "Structual object-oriented video segmentation and representation algorithm," in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 78-82 Nov. 1998.
  45. H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa: "Hybrid VLSI architecture for motion compensation and texture mapping," in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 383-386, Nov. 1998.
  46. H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura: "Matrix-vector multiplier module for natural/synthetic hybrid video coding," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 631-634, Nov. 1998.
  47. K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng: "Multi-mode and multi-level technologies for FeRAM embedded reconfigurable hardware," in IEEE Int'l Solid-State Circuits Conference (ISSCC) Diegest of Technical Papers, pp. 106-107, Feb. 1999.
  48. G. Fujita, H. Okuhata, M. H. Miki, K. Matsumura, T. Onoye, and I. Shirakawa: "Low-power architecture of H.324 codec dedicated to mobile computing," in Proc. EUROMEDIA, pp. 145-149, April 1999.
  49. M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami: "Recursive maximum likelihood decoder for high-speed satellite communication," in Proc. International Symposium on Circuits and Systems, pp. 572-575, June 1999.
  50. H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa: "Hybrid media-processor core for natural and synthetic video decoding," in Proc. International Symposium on Circuits and Systems, pp. 275-278, June 1999.
  51. B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa: "Array macro cell architecture for low-power NMOS 4-phase dynamic logic," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 561-564, July 1999.
  52. M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa: "Pipelined implementation of JBIG arithmetic coder," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 470-473, July 1999.
  53. R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa: "Embedded zerotree wavelet based algorithm for video compression," in Proc. IEEE Region 10 Conference, pp. 1343-1346, Sept. 1999.
  54. M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa: "Layout generation for low-power NMOS 4-phase dynamic logic array," in Proc. IEEE Region 10 Conference, pp. 872-875, Sept. 1999.
  55. M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa: "High-speed implementation of JBIG arithmetic coder," in Proc. IEEE Region 10 Conference, pp. 1291-1294, Sept. 1999.
  56. R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa: "Architecture of embedded zerotree wavelet based real-time video coder," in Proc. ASIC/SOC Conference, pp. 137-141, Sept. 1999.
  57. R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa: "Video coding algorithm based on modified discrete wavelet transform," in Proc. Nonlinear Theory and Its Application, pp. 251-254, Nov. 1999.
  58. M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa: "Layout generation of array cell for NMOS 4-phase dynamic logic," in Proc. Asia and South Pacific Design Automation Conference, pp. 529-532, Jan. 2000.
  59. Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa: "Chameleon: A dynamically reconfigurable hardware-based cryptosystem," in Proc. EUROMEDIA, pp. 90-94, May 2000.
  60. D. Murakami, T. Izumi, T. Onoye, and Y. Nakamura: "A hardware algorithm of dynamic area allocation to circuits for plastic cell architecture," in Proc. EUROMEDIA, pp. 85-89, May 2000.
  61. R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa: "VLSI implementation of a realtime wavelet video coder," in Proc. Custom Integrated Circuits Conference, pp. 543-546, May 2000.
  62. Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa: "VLSI implementation of dynamically reconfigurable hardware-based cryptosystem," in Symposium on VLSI Circuits Digest of Technical Papers, pp. 204-205, June 2000.
  63. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "Low power DSP implementation of 3D sound localization," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 253-256, July 2000.
  64. W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa: "3D acoustic image localization algorithm by embedded DSP," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 264-267, July 2000.
  65. R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa: "Discrete cosine transformer with variable-length basis vector for MPEG-4 video codec," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 811-814, July 2000.
  66. S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa: "VLSI implementation of portable MPEG-4 audio decoder," in Proc. ASIC/SOC Conference, pp. 80-84, Sept. 2000.
  67. Y. Dong, R. Y. Omaki, T. Onoye, and I. Shirakawa: "VLSI implementation of a reduced memory bandwidth realtime EZW video coder," in Proc. International Conference on Image Processing, pp. 126-129, Sept. 2000.
  68. Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa: "A dynamically reconfigurable hardware-based cipher chip," in Proc. Asia and South Pacific Design Automation Conference, pp. 11-12, Jan. 2001.
  69. R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa: "Realtime wavelet video coder based on reduced memory accessing," in Proc. Asia and South Pacific Design Automation Conference, pp. 15-16, Jan. 2001.
  70. Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa: "A high performance burst mode approach for 128-bit block ciphers," in Proc. EUROMEDIA, pp. 146-150, April 2001.
  71. M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa: "Two-dimensional array layout for low power NMOS 4-phase dynamic logic," in Proc. International Conference Electronics Packaging, pp. 417-421, April 2001.
  72. Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa: "VLSI architecture of dynamically reconfigurable hardware-based cipher," in Proc. International Symposium on Circuits and Systems, pp. IV.734-IV.737, May 2001.
  73. K. Chikamura, T. Izumi, T. Onoye, and Y. Nakamura: "IEEE1394 system simulation environment and a eesign of its link layer controller," in Proc. International Symposium on Circuits and Systems, pp. V.1-V.4, May 2001.
  74. H. Tsutsui, K. Hiwada, T. Izumi, T. Onoye, and Y. Nakamura: "A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression," in Proc. International Symposium on Circuits and Systems, pp. V.203-V.206, May 2001.
  75. H. Okada, H.S. Song, G. Fujita, T. Onoye, and I. Shirakawa: "Error detection based on check marker embedding for MPEG-4 video coding," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 96-99, July 2001.
  76. H.S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa: "Error concealment algorithm by motion estimation method for MPEG-4 video decoder," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 104-107, July 2001.
  77. T. Song, G. Fujita, T. Onoye, and I. Shirakawa: "Low power architecture for H.263 version 2 codec," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 620-623, July 2001.
  78. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "DSP implementation of realtime 3D sound localization algorithm," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1140-1143, July 2001.
  79. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "Low power DSP implementation of 3D sound localization for monaural sound source," in Proc. World Multiconference on Systemics, Cybernetics and Informatics, pp. 173-177, July 2001.
  80. H. Tsutsui, T. Masuzaki, M. Oyamatsu, T. Izumi, T. Onoye, and Y. Nakamura: "Design of JPEG2000 encoder for fully scalable image coding," in Proc. World Multiconference on Systemics, Cybernetics and Informatics, pp. 546-551, July 2001.
  81. M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa: "Two-dimensional array layout for NMOS 4-phase dynamic logic," in Proc. International Conference on Electronics, Circuits and Systems, pp. 589-592, Sept. 2001.
  82. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "DSP implementaion of 3D sound localization algorithm for monaural sound source," in Proc. International Conference on Electronics, Circuits and Systems, pp. 1061-1064, Sept. 2001.
  83. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "DSP implementation of low computational 3D sound localization algorithm," in Proc. Workshop on Signal Processing Systems, Design and Implementation, pp. 109-116, Sept. 2001.
  84. Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa: "VLSI implementation of high performance burst mode for 128-bit block ciphers," in Proc. ASIC/SOC Conference, pp. W1.1.1-W1.1.5, Sept. 2001.
  85. T. Okamoto, K. Sakai, A. Tomita, S. Sugimoto, T. Izumi, T. Onoye, and Y. Nakamura: "C-based design automation environment for plastic cell architecture," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 45-49, Oct. 2001.
  86. H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa: "An architecture level power estimation method for embedded systems," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 78-85, Oct. 2001.
  87. X. Li, T. Fukushima, T. Izumi, T. Onoye, and Y. Nakamura: "A HW/SW design of an MP3 decoder," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 327-331, Oct. 2001.
  88. Z. Andales, Y. Mituyama, T. Onoye, and I. Shirakawa: "System performance evaluation of high-speed burst mode for 128-bit block ciphers," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 332-339, Oct. 2001.
  89. M. Kimura, M.H. Miki, T. Onoye, and I. Shirakawa: "High performance Java execution for embedded systems," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 346-350, Oct. 2001.
  90. M. Ise, Y. Uchida, T. Onoye, and I. Shirakawa: "System-on-a-chip architecture for W-CDMA baseband modem LSI," in Proc. International Conference on ASIC, pp. 364-369, Oct. 2001.
  91. M.H. Miki, M. Kimura, T. Onoye, and I. Shirakawa: "High performance Java hardware engine and software kernel for embedded systems," in Proc. International Conference on Very Large Scale Integration, pp. 365-369, Dec. 2001.
  92. M. Kimura, M.H. Miki, T. Onoye, and I. Shirakawa: "A Java accelerator for high performance embedded systems," in Proc. International Conference of Massively Parallel Computing Systems, pp. 3.2.1-3.2.6, April 2002.
  93. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "DSP implementation of realtime 3D sound synthesis algorithm for monaural sound source," in Proc. EUROMEDIA, pp. 123-127, April 2002.
  94. H. Tsutsui, T. Masuzaki, M. Oyamatsu, T. Izumi, T. Onoye, and Y. Nakamura: "JPEG2000 fully scalable image encoder by configurable processor," in Proc. EUROMEDIA, pp. 168-172, April 2002.
  95. Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa: "Burst mode: A new acceleration mode for 128-bit block ciphers," in Proc. Custom Integrated Circuits Conference, pp. 151-154, May 2002.
  96. Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, and T. Chiba: "Error correction block based ARQ protocol for wireless digital video transmission," in Proc. International Symposium on Circuits and Systems, pp. I.605-I.608, May 2002.
  97. H. Yamamoto, K. Chikamura, T. Izumi, T. Onoye, and Y. Nakamura: "An intelligent IEEE1394 HUB architecture," in Proc. International Symposium on Circuits and Systems, pp. II.249-II.252, May 2002.
  98. Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai: "VLSI architecture of burst mode acceleration for 128-bit block ciphers," in Proc. International Symposium on Circuits and Systems, pp. II.344-II.347, May 2002.
  99. H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa: "Power Estimation at Architecture Level for Embedded Systems," in Proc. International Symposium on Circuits and Systems, pp. II.476-II.479, May 2002.
  100. Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai: "VLSI architecture of digital matched filter and prime interleaver for W-CDMA," in Proc. International Symposium on Circuits and Systems, pp. III.269-III.272, May 2002.
  101. T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura: "JPEG2000 adaptive rate control for embedded systems," in Proc. International Symposium on Circuits and Systems, pp. IV.333-IV.336, May 2002.
  102. W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa: "`Out-of-head' acoustic field enhancement for stereo headphones by embedded DSP," in International Conference on Consumer Electronics Digest of Technical Papers, pp. 222-223, June 2002.
  103. Y. Ohtani, N. Kawahara, T. Onoye, I. Shirakawa, and T. Chiba: "MAC LSI design for wireless MPEG2 transmission over IEEE802.11b PHY," in International Conference on Consumer Electronics Digest of Technical Papers, pp. 242-243, June 2002.
  104. A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa: "A hardware implementation of Ogg Vorbis audio decoder with embedded processor," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 94-97, July 2002.
  105. S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "Synthesis of 3D sound movement by embedded DSP," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 117-120, July 2002.
  106. H. Okada, A.E. Shiitev, H.S. Song, G. Fujita, T. Onoye, and I. Shirakawa: "Digital watermark based error detection for MPEG-4 bitstream error," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 152-155, July 2002.
  107. T. Kaya, R. Miyamoto, T. Onoye, and I. Shirakawa: "Embedded system for video coding with logic-enhanced DRAM and configurable processor," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 216-219, July 2002.
  108. H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa: "Hybrid error concealment algorithm for MPEG-4 videodecoders," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 611-614, July 2002.
  109. T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura: "Adaptive rate control for JPEG2000 image coding in embedded systems," in Proc. International Conference on Image Processing, vol. 3, pp. 77-80, Sept. 2002.
  110. A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa: "VLSI implementation of Ogg Vorbis decoder for embedded applications," in Proc. ASIC/SOC Conference, pp. 20-24, Sept. 2002.
  111. H. Yamamoto, K. Chikamura, A. Shigiya, K. Tsujino, T. Izumi, T. Onoye, and Y. Nakamura: "System-level design of IEEE1394 bus segment bridge," in Proc. International Symposium on System Synthesis, pp. 74-79, Oct. 2002.
  112. K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa: "Realtime face object extraction algorithm for video phone," in Proc. Asia-Pacific Conference on Circuits and Systems, vol. 1, pp. 35-38, Dec. 2002.
  113. Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa: "Implementation of wireless MPEG2 transmission system using IEEE 802.11b PHY," in Proc. Asia-Pacific Conference on Circuits and Systems, vol. 1, pp. 39-44, Dec. 2002.
  114. H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, "High speed JPEG2000 encoder by configurable processor," in Proc. Asia-Pacific Conference on Circuits and Systems, vol. 1, pp. 45-50, Dec. 2002.
  115. N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa: "Embedded implementation of acousitic field enhancement for stereo headphones," in Proc. Asia-Pacific Conference on Circuits and Systems, vol. 1, pp. 50-54, Dec. 2002.
  116. T. Yuasa, A. Tomita, T. Izumi, T. Onoye, and Y. Nakamura: "An approach for circuit size reduction by variable reordering for PCA-chip2," in Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.217-221, April 2003.
  117. T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa: "VLSI architecture for MPEG-4 core profile codec core," in Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.365-371, April 2003.
  118. Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura: "Scalable design framework for JPEG2000 encoder architecture," in Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.372-376, April 2003.
  119. N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa: "Low cost approach to acoustic field enhancement for stereo headphones," in Proc. EUROMEDIA, pp. 32-36, April 2003.
  120. T. Yuasa, Y. Soga, T. Izumi, T. Onoye, and Y. Nakamura: "An improved communication channel in dynamic reconfigurable device for multimedia applications," in Proc. EUROMEDIA, pp. 152-157, April 2003.
  121. S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "Interactive interface of realtime 3D sound movement for embedded applications," in Proc. International Symposium on Circuits and Systems, pp. 520-523, May 2003.
  122. Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura: "Design framework for JPEG2000 encoding system architecture," in Proc. International Symposium on Circuits and Systems, pp. 740-743, May 2003.
  123. T. Izumi, K. Tada, T. Yuasa, T. Onoye, and Y. Nakamura: "An adaptive load distribution model for self-reconfigurable logic device," in Proc. Northeast Workshop on Circuit and Systems, pp. 13-16, June 2003.
  124. N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa: "Embedded implementation of acoustic field enhancement for stereo sound sources," in International Conference on Consumer Electronics Digest of Technical Papers, pp. 256-257, June 2003.
  125. A. Kotani, Y. Asai, Y. Nakamura, S. Okada, N. Koyama, K. Yamane, Y. Okano, Y. Mitsuyama, and T. Onoye: "Visibility font technology on high resolution color LCD LCFONT.C," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 535-538, July 2003.
  126. S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and Isao Shirakawa: "Low power Ogg Vorbis decoder by embedded processor," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 565-568, July 2003.
  127. T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa: "Feature extraction of head-related transfer function for 3D sound movement," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 685-688, July 2003.
  128. H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa: "Efficient error recovery scheme for MPEG-4 video coding," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1328-1331, July 2003.
  129. K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa: "Modified snake: real-time face object extraction for video phone," in Proc. IEEE International Conference on Image Processing, pp. 873-876, Sept. 2003.
  130. M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa: "Implementation of W-CDMA channel codec by configurable processors," in Proc. Sixth Baiona Workshop on Signal Processing in Communications, pp. 205-210, Sept. 2003.
  131. K. Tsujino, A. Shigiya, T. Izumi, T. Onoye, Y. Nakamura, and W. Kobayashi: "A DSP-based 3-D sound synthesis system for moving sound images," in Proc. GAME-ON Conference, pp. 23-25, Nov. 2003.
  132. K. Tsujino, A. Shigiya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura: "An implementation of moving 3-D sound synthesis system based on floating point DSP," in Proc. IEEE International Symposium on Signal Processing and Information Technology, pp. WA4-8.1-WA4-8.4, Dec. 2003.
  133. A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa: "SoC design of Ogg Vorbis decoder using embedded processor," in Proc. Computing Frontier Conference, pp. 481-487, April 2004.
  134. H. Sugita, Q.-M. Vu, T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura: "JPEG2000 high-speed progressive decoding scheme," in Proc. IEEE International Symposium on Circuits and Systems, pp. 873-876, May 2004.
  135. T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa: "Embedded system implementation of scalable and object-based video coding," in Proc. World Automation Congress, pp. 076.1-076.8, June 2004.
  136. Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa: "Architecture of Turbo decoder for W-CDMA by configurable processor," in Proc. International Technical Conference on Circuits/Systems, Computersand Communications, pp. 7F2P-27.1-7F2P-27.4, July 2004.
  137. Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa: "Embedded architecture of IEEE802.11i cipher algorithms," in Proc. IEEE International Symposium on Consumer Electronics, pp. 241-246, Sept. 2004.
  138. S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa: "C-based hardware design of IMDCT accelerator for Ogg Vorbis decoder," in Proc. European Signal Processing Conference, pp. 1361-1364, Sept. 2004.
  139. H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Nakamura: "Scalable design framework for JPEG2000 system architecture," in Proc. Asia-Pacific Computer Systems Architecture Conference, pp. 296-308, Sept. 2004.
  140. J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, "A scalable approach for estimation of focus of expansion," in Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pp. 6-11, Sept. 2004.
  141. N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa: "VLSI implementation of a 3D sound movement system," in Proc. Workshop on Synthesis And System Integration of Mixed Information technologies, pp.121-125, Oct. 2004.
  142. N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa: "VLSI implementation of 3D sound image movement for embedded systems," in Proc. IEEE Region 10 Conference, pp. 21-24, Nov. 2004.
  143. K. Tsujino, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura: "Realtime filter redesign for interactive 3-D sound systems," in Proc. IEEE Region 10 Conference, pp. 124-127, Nov. 2004.
  144. R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura: "Video quality enhancement for Motion JPEG2000 encoding based on the human visual system," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 1161-1164, Dec. 2004.
  145. T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa: "Embedded 3D sound movement system based on feature extraction of head-related transfer function," International Conference on Consumer Electronics Digest of Technical Papers, pp. 7.1-7.2, Jan. 2005.
  146. R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura: "High quality motion JPEG2000 coding scheme based on the human visual system," in Proc. IEEE Int’l Symp. Circuits and Systems, pp. 2096-2099, May 2005.
  147. T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai: "3D sound movement system for embedded applications," in Proc. IEEE Int’l Symp. Circuits and Systems, pp. 5345-5348, May 2005.
  148. Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa: "An approach for area-efficient coarse-grained reconfigurable architecture dedicated to media processing," in Proc. International Technical Conference of Circuits/Systems, Computers and Communications, pp. 131-132, July 2005.
  149. H. V. Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa: "Fast human object extraction method based on color space segmentation for mobile systems," in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp.1015-1016, July 2005.
  150. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Measurement and analysis of delay variation due to inductive coupling," in Proc. IEEE Custom Integrated Circuits Conference, pp.305-308, 2005.
  151. Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa: "A low-complexity FEC assignment scheme for Motion JPEG2000 over wireless network," in International Conference on Consumer Electronics Digest of Technical Papers, pp. 391-392, Jan. 2006.
  152. K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye: "A gate delay model focusing on current fluctuation over wide-range of process and environmental variability," in Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 59-64, Feb. 2006.
  153. Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa: "Domain-specific reconfigurable architecture for media processing," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2006), pp. 322-327, April 2006.
  154. A. Kotani, Y. Tanemura, Y. Mitsuyama, Y. Asai, Y. Nakamura, and T. Onoye: "Contour-based gravity center evaluation of characters," in Proc. EUROMEDIA, pp. 15-20, April 2006.
  155. K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura: "Automated design of digital filters for 3-D sound localization in embedded applications," in Proc. International Conf. Audio, Speech, and Signal Processing (ICASSP2006), pp. V.349-V.352, May 2006.
  156. H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and Y. Nakamura: "Efficient memory architecture for JPEG2000 entropy codec," in Proc. International Symposium on Circuits and Systems, pp. 2881-2884, May 2006.
  157. A. Kosaka and T. Onoye: "Pipeline processing of continuous speech recognition algorithm for embedded system implementation," in Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. II, pp. 373-376, July 2006.
  158. F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura: "A JPEG coding scheme for high fidelity images by halftoning less signification extra bits," in Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. III, pp. 97-100, July 2006.
  159. Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye: "Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation," in Proc. Custom Integrated Circuits Conference, pp. 861-864, Sept. 2006.
  160. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Measurement of inductive coupling effect on timing in 90nm global interconnects," in Proc. Custom Integrated Circuits Conference, pp. 721-724, Sept. 2006.
  161. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Quantitative prediction of on-chip capacitive and inductive crosstalk noise and discussion on wire cross-sectional area toward inductive crosstalk free interconnects," in Proc. International Conference on Computer Design, pp. 70-75, Oct. 2006.
  162. J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura: "Probabilistic pedestrian tracking based on a skeleton model," in Proc. International Conference on Image Processing, pp. 2825-2828, Oct. 2006.
  163. K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye: "A gate delay model focusing on current fluctuation over wide-range of process and environmental variability," in Proc. International Conference on Computer-Aided Design, pp. 47-53, Nov. 2006.
  164. R. Hashimoto, K. Katou, G. Fujita, and T. Onoye: "VLSI architecture of H.264 block size decision based on rate-distortion optimization," in Proc. International Symposium on Intelligent Signal Processing and Communication Systems, pp. 618-621, Dec. 2006.
  165. K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi: “An energy-efficient architecture of wireless home network based on MAC broadcast and transmission power control,” in International Conference on Consumer Electronics Digest of Technical Papers, P1-20, Jan. 2007.
  166. K. Shinkai, M. Hashimoto, and T. Onoye: "Future prediction of self-heating in short intra-block wires," in Proc. International Symposium on Quality Electronic Design, pp. 660-665, March 2007.
  167. M.N.B. Mohd Nor, T. Matsumura, and T. Onoye: "Direction of arrival estimation Improvement of speech on a two-microphone array," in Proc. IASTED International Conf. Signal and Image Processing, 576.115, August 2007.
  168. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Dynamic supply noise measurement with all digital gated oscillator for evaluating decoupling capacitance effect," in Proc. IEEE Custom Integrated Circuits Conference, pp. 783-786, September 2007.
  169. K. Takahashi, Y. Nozato, H. Okuhata, and T. Onoye: "VLSI architecture for real-time retinex video image enhancement," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 81-86, October 2007.
  170. K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "A study on body-biasing layout style focusing on area efficiency and speed controllability," in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 233-237, October 2007.
  171. R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye: "Implementation of object attention based on multi-agent attractor selection," in Proc. International Workshop on Smart Info-Media Systems in Bangkok, pp. 23-33, November 2007.
  172. R. Hashimoto, K. Kato, G. Fujita, and T. Onoye: "VLSI architecture of H.264 RDO-based block size decision for 1080 HD," in Proc. Picture Coding Symposium, ThPM4.9, November 2007.
  173. Y. Manabe, J. Hara, and T. Onoye: "JPM-based differential image storage scheme for image revision management system," in Proc. IIEEJ Image Electronics and Visual Computing Workshop 2007, 2C-2, November 2007.
  174. J. Hara, B.R. Mohsen, and T. Onoye: "Structure representation and reference method for JPEG 2000 family formats," in Proc. IIEEJ Image Electronics and Visual Computing Workshop 2007, 2C-3, November 2007.
  175. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification," in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108, January 2008.
  176. S. Abe, M. Hashimoto, and T. Onoye: "Clock skew evaluation considering manufacturing variability in mesh-style clock distribution," in Proc. International Sympos. Quality Electronic Design (ISQED), pp. 520-525, March 2008.
  177. H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa: "Video image enhancement scheme for high resolution consumer devices," in Proc. International Symposium on Communications, Control, and Signal Processing, pp. 639-644, March 2008.
  178. K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Experimental study on body-biasing layout style - Negligible area overhead enables sufficient speed controllability -," in Proc. Great Lakes Symposium on VLSI, pp. 387-390, May 2008.
  179. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits," in Proc. International Symposium on Low Power Electronics and Design, pp. 3-8, August 2008.
  180. M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi: "A 3D sound localization method for multiple sound sources based on Fuzzy clustering," in Proc. International Workshop on Smart Info-Media Systems in Bangkok, pp. 133-138, December 2008.
  181. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction," in Proc. Asia and South Pacific Design Automation Conference, pp. 266-271, January 2009.
  182. M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi: "An embedded sound localization system for multiple sources by Fuzzy clustering with spatial constraints," in Proc. International Workshop on Nonlinear Circuits and Signal Processing, pp. 257-260, March 2009.
  183. R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei: "Implementation of OFDM baseband transceiver with dynamic spectrum access for cognitive radio systems," in Proc. International Symposium on Communication and Information Technology, pp. 658-663, September 2009.
  184. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits," in Proc. IEEE Custom Integrated Circuits Conference, pp. 215-218, September 2009.
  185. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits," in Proc. Asia and South Pacific Design Automation Conference, pp. 361-362, January 2010.
  186. S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye: "Clock skew reduction by self-compensating manufacturing variability with on-chip sensors," in Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 89-94, March 2010.
  187. R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye: "Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution," in Proc. International Symposium on Quality Electronic Design, pp. 839-844, March 2010.
  188. H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye: "Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration," in Proc. International Symposium on Quality Electronic Design, pp. 646-651, March 2010.
  189. Y. Kawamura, Y. Manabe, T. Onoye, K. Ohara, H. Okada, and I. Keshi: "Implementation of simultaneous video decoding on multicore processor," in Proc. International Symposium on Communications, Control and Signal Processing, pp. 1-4, March 2010.
  190. D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye: "A 16-bit RISC processor with 4.18pJ/cycle at 0.5V operation," in Proc. IEEE COOL Chips, p. 190, April 2010.
  191. Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye: "Measurement of on-chip I/O power supply noise and correlation verification between noise magnitude and delay increase due to SSO," in Proc. IEEE Wrokshop on Signal Propagation on Interconnects, pp. 19-20, May 2010.
  192. S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye: "Clock skew reduction by self-compensating manufacturing variability with on-chip sensors," in Proc. Great Lakes Symposium on VLSI, pp. 197-202, May 2010.
  193. L. M. Handaya, M. Okada, T. Onoye, and W. Kobayashi: "Improvement of frontal localization with complement of multiple delayed sounds," in Proc. International Workshop on Information Communication Technology, pp. S1.5.1-S1.5.4, August 2010.
  194. Y. Takai, M. Hashimoto, and T. Onoye: "Evaluation of power gating structures focusing on power supply noise with measurement and simulation," in Proc. Electrical Performance of Electronic Packaging and Systems, pp. 213-216, October 2010.
  195. M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei: "VLSI design of OFDM baseband transceiver with dynamic spectrum access," in Proc. International Symposium on Intelligent Signal Processing and Communication Systems, pp. 329-332, December 2010.
  196. T. Amaki, M. Hashimoto, and T. Onoye: "Jitter amplifier for oscillator-based true random number generator," in Proc. Asia and South Pacific Design Automation Conference, pp. 81-82, January 2011.
  197. T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "A design procedure for oscillator-based hardware random number generator with stochastic behavior modeling," in Proc. International Workshop on Information Security Applications, pp. 107-121, January 2011.
  198. T. Maeno, H. Tsutsui, and T. Onoye: "Hardware implementation of real-time motion adaptive deinterlacing based on inpainting," in Proc. International Conference on Embedded Systems and Intelligent Technology, pp. 159-164, February 2011.

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