論文誌

[1] T. Enami, T. Sato, and M. Hashimoto, "Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2261--2271, December 2012.

[2] T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, "Impact of Self-Heating in Wire Interconnection on Timing," IEICE Trans. on Electronics, volume E93-C, number 3, pages 388--392, March 2010.

[3] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for Cmos Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , volume 29, number 2, pages 250--260, February 2010.

[4] T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, "An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3016--3023, December 2009.

[5] A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto, "Interconnect Modeling: a Physical Design Perspective (Invited)," IEEE Transactions on Electron Devices, volume 56, number 9, pages 1840--1851, September 2009.

[6] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, "Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 92-A, number 4, pages 990--997, April 2009.

[7] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," IEICE Trans. on Information and Systems , volume E91-D, number 3, pages 655--660, March 2008.

[8] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Trans. on Circuits and Systems—II: Express Briefs, volume 54, number 10, pages 868-872, October 2007.

[9] T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto, "On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3491-3499, December 2006.

[10] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment for Minimizing Supply Voltage Drop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3429-3436, December 2005.

[11] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005.

[12] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa, "Object Sharing Scheme for Heterogeneous Environment," in IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 4, pages 813--821, April 2003.

国際会議

[1] S. Watanabe, M. Hashimoto, and T. Sato, "A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 401--407, March 2009.

[2] T. Enami, M. Hashimoto, and T. Sato, "Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis," In Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 420-425, November 2008.

[3] S. Watanabe, M. Hashimoto, and T. Sato, "Cascading Dependent Operations for Mitigating Timing Variability," In Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008.

[4] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proc.~IEEE Custom Integrated Circuits Conference, pages 861--864, September 2006.

[5] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 723-728, January 2005.

[6] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1098-1101, January 2005.

[7] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005.

[8] T. Sato, M. Hashimoto, and H. Onodera, "An Ir-Drop Minimization by Optimizing Number and Location of Power Supply Pads," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 66-72, October 2004.

[9] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, O. Tsumori, K. Hanada, T. Chiba, and I. Shirakawa, "OCEAN: Object Communication Environment for Arbitrary Network," In in Proc. IEEE International Conference on Distributed Computing Systems Workshops, pages 162--166, July 2002.

研究会等発表論文

[1] 小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史, 尾上孝雄, "電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法," 信学技報, CPM2006-132, ICD2006-174, pages 19--23, 2007年1月.