論文誌

[1] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator," IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, volume E98-A, number 12, pages 2607--2613, December 2015.

[2] S. Hirokawa, R. Harada, M. Hashimoto, and T. Onoye, "Characterizing Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4-V Srams," IEEE Transactions on Nuclear Science, April 2015.

[3] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Transactions on Nuclear Science, volume 59, number 6, pages 2791--2795, December 2012.

[4] S. Kimura, M. Hashimoto, and T. Onoye, "A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2292--2300, December 2012.

[5] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume 93-A, number 12, pages 2399-2408, December 2010.

[6] S. Ninomiya and M. Hashimoto, "Accuracy Enhancement of Grid-Based Ssta by Coefficient Interpolation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2441--2446, December 2010.

[7] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 4, pages 541-553, April 2009.

[8] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3481-3487, December 2008.

[9] M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of LCD Driver Circuit for Technology Migration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2712--2717, December 2007.

[10] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3538--3545, December 2006.

[11] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3538-3545, December 2006.

[12] T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M Hashimoto, "Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3666-3670, December 2006.

国際会議

[1] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, "Stochastic Timing Error Rate Estimation under Process and Temporal Variations," In Proceedings of International Test Conference (ITC), October 2015.

[2] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced Seu and Mcu Rate Characterization and Analysis of Sotb and Bulk Srams at 0.3v Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.

[3] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 Nm Sram," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.

[4] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 Nm Bulk Cmos," Proceedings of International Reliability Physics Symposium (IRPS), April 2015.

[5] S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, and T. Onoye, "3d Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method," Proceedings of Virtual Reality Conference (VR), March 2015.

[6] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 731--736, January 2015.

[7] R. Harada, S. Hirokawa, and M. Hashimoto, "Measurement of Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4 V Srams," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.

[8] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313-316, November 2013.

[9] S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, "Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing," In Proc. International Conference on Computer-Aided Design (ICCAD), pages 107-114, November 2013.

[10] Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, and S. Nassif, "Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator," Proceedings of IEEE European Test Symposium (ETS), pages 106--111, May 2013.

[11] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Nuclear and Space Radiation Effects Conference, July 2012.

[12] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 283--289, February 2012.

[13] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 46--51, April 2011.

[14] M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, "VLSI Design of OFDM Baseband Transceiver with Dynamic Spectrum Access," In Proc. of the 18th International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2010), pages 329-332, December 2010.

[15] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.

[16] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 41-46, March 2010.

[17] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.

[18] R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, "Implementation of Ofdm Baseband Transceiver with Dynamic Spectrum Access for Cognitive Radio Systems," In Proc. of 9th International Symposium on Communication and Information Technology (ISCIT2009), pages 658-663, September 2009.

[19] S. Ninomiya and M. Hashimoto, "Enhancement of Grid-Based Spatially-Correlated Variability Modeling for Improving Ssta Accuracy," In Proceedings of IEEE International SOC Conference (SOCC), pages 337--340, September 2009.

[20] S. Watanabe, M. Hashimoto, and T. Sato, "A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 401--407, March 2009.

[21] S. Watanabe, M. Hashimoto, and T. Sato, "Cascading Dependent Operations for Mitigating Timing Variability," In Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008.

[22] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays," In In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.

[23] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," In Proc. ACM International Symposium on Physical Design, pages 160-167, April 2008.

[24] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," In Proc. International Symposium on Quality Electronic Design (ISQED), pages 520-525, March 2008.

[25] T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of Lcd Driver Circuit for Technology Migration," In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), volume 1, I25--I28, July 2006.

[26] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design for Liquid Crystal Displays," In Proceedings of IEEE International Region 10 Conference, 1C-03.3, 2005.

[27] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Scheme for Sampling Switch in Active Matrix LCD," In Proceedings of European Conference on Circuit Theory and Design, 3e-212, 2005.

[28] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design for Liquid Crystal Displays," In Proceedings of IEEE International Region 10 Conference, November 2005.

[29] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Scheme for Sampling Switch in Active Matrix Lcd," In A Design Scheme for Sampling Switch in Active Matrix LCD, August 2005.

[30] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System LCD Circuits," In in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005), pages 160--163, April 2005.

[31] S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa, "VLSI Implementation of Portable MPEG-4 Audio Decoder," In in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA, pages 80--84, September 2000.

研究会等発表論文

[1] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," 電子情報通信学会 VLSI設計技術研究会, March 2015.