論文誌

[1] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3461-3464, December 2008.

[2] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," IEICE Trans. on Information and Systems , volume E91-D, number 3, pages 655--660, March 2008.

[3] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2661-2668, December 2007.

[4] M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, volume E80-A, number 10, pages 1853-1860, October 1997.

国際会議

[1] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," In Proc. IEEE European Solid-State Device Research Conference, pages 115-118, September 2007.

[2] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1098-1101, January 2005.

[3] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 814-820, November 2004.

[4] N. Ishiura, T. Watanabe, and M. Yamaguchi, "A Code Generation Method for Datapath Oriented Application Specific Processor Design," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pages 71--78, April 2000.

[5] N. Ishiura and M. Yamaguchi, "Operation Binding for Retargetable Compilers Minimizing Clock Cycles," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pages 705--708, July 1999.

[6] N. Ishiura, M. Yamaguchi, and T. Kambe, "A Graph-Based Algorithm of Operation Binding for Compilers Targeting Heterogeneous Datapath," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pages 395--398, November 1998.

[7] N. Ishiura, M. Yamaguchi, and N. Nitta, "Field Partitioning Algorithms for Compression of Instruction Codes of Application Specific VLIW Processors," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1387--1390, July 1998.

[8] M. Yamaguchi, N. Ishiura, and T. Kambe, "A Binding Algorithm for Retargetable Compilation to Non-Orthogonal Datapath Architectures," In in Proc. International Symposium on Circuits and Systems, WPA4-4, June 1998.

[9] M. Yamaguchi, N. Ishiura, and T. Kambe, "Binding and Scheduling Algorithms for Highly Retargetable Compilation," In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pages 93-98, February 1998.

[10] N. Ishiura and M. Yamaguchi, "Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning," In in Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), pages 105-109, December 1997.

[11] M.Yamaguchi, T. Nakaoka, A. Yamada, and T. Kambe, "An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint," In in Proc. IEEE International Symposium on Circuits and Systems, pages 1584-1587, June 1997.

[12] M. Yamaguchi, A. Yamada, T. Nakaoka, and T. Kambe, "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint," In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pages 503-508, January 1997.