論文誌

[1] I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, "A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, volume E80-A, number 12, pages 2589-2599, December 1997.

[2] Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, "Automatic Layout Recycling Based on Layout Description and Linear Programming," in Proc. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, volume 15, number 8, pages 959-967, August 1996.

国際会議

[1] T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai, "3D Sound Movement System for Embedded Applications," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2005), Kobe, Japan, pages 5345-5348, May 2005.

[2] Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, "VLSI Architecture of Digital Matched Filter and Prime Interleaver for W-CDMA," In Proc. IEEE International Symposium on Circuits and Systems (ISCAS2002), Phoenix, Arizona, volume III, pages 269--272, May 2002.

[3] Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, "VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers," In ibid, volume II, pages 344--347, May 2002.

[4] I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, "A Fast Minimun Cost Flow Algofithm for VLSI Layout Compaction," In in Proc. IEEE International Symposium on Circuits and Systems, pages 1672-1675, June 1997.

[5] Y. Shigehiro, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, "A Fast Minimum Cost Flow Algorithm and Its Application to VLSI Layout Compaction," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 951-954, July 1996.