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| E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, "Design of Generic Hardware for Soft Cascade-Based Linear Svm Classification," In International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 257-262, November 2015. | |
| ID | 825 |
| 分類 | 国際会議 |
| タグ | |
| 表題 (title) |
Design of Generic Hardware for Soft Cascade-Based Linear Svm Classification |
| 表題 (英文) |
Design of Generic Hardware for Soft Cascade-Based Linear Svm Classification |
| 著者名 (author) |
E. Aliwarga,J. Yu,M. Hatanaka,T. Onoye |
| 英文著者名 (author) |
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| 編者名 (editor) |
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| 編者名 (英文) |
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| キー (key) |
Eric Aliwarga, jaehoon Yu, Masahide Hatanaka, Takao Onoye |
| 書籍・会議録表題 (booktitle) |
International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) |
| 書籍・会議録表題(英文) |
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| 巻数 (volume) |
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| 号数 (number) |
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| ページ範囲 (pages) |
257-262 |
| 組織名 (organization) |
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| 出版元 (publisher) |
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| 出版元 (英文) |
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| 出版社住所 (address) |
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| 刊行月 (month) |
11 |
| 出版年 (year) |
2015 |
| 採択率 (acceptance) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
Support Vector Machine is renowned as a powerful machine learning algorithm for many classification problems. However, among all the works proposed for SVM hardware implementation, a lot of them are designed with predefined settings for specific objective, rendering them usable only for single or few purposes. This paper presents an SVM hardware architecture capable of classifying input data with arbitrary vector dimensionality and arbitrary precision, resulting in a generic support vector machine capable of classifying various targets. The proposed architecture also employs a speed-up method called soft cascade algorithm to enhance its performance. To assess its hardware implementation, it is synthesized in two styles using Xilinx FPGA and NanGate Open Cell Library. The results show a feasible circuit scale implementation, and when used for CoHOG pedestrian detection, the proposed hardware architecture is estimated to be capable of classifying up to 79 VGA images per second on FPGA and up to 35 HD images per second on 45nm process technology circuit, even under the condition that the architecture is not designed specifically for the aforementioned purpose. |
| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@inproceedings{id825,
title = {Design of Generic Hardware for Soft Cascade-Based Linear SVM Classification},
author = {E. Aliwarga and J. Yu and M. Hatanaka and T. Onoye},
booktitle = {International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)},
pages = {257-262},
month = {11},
year = {2015},
}
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