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| T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, 60(6), pp. 4362--4367, December 2013. | |
| ID | 719 |
| 分類 | 論文誌 |
| タグ | |
| 表題 (title) |
Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch |
| 表題 (英文) |
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| 著者名 (author) |
T. Uemura,T. Kato,H. Matsuyama,M. Hashimoto |
| 英文著者名 (author) |
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| キー (key) |
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| 定期刊行物名 (journal) |
IEEE Transactions on Nuclear Science |
| 定期刊行物名 (英文) |
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| 巻数 (volume) |
60 |
| 号数 (number) |
6 |
| ページ範囲 (pages) |
4362--4367 |
| 刊行月 (month) |
12 |
| 出版年 (year) |
2013 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@article{id719,
title = {Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch},
author = {T. Uemura and T. Kato and H. Matsuyama and M. Hashimoto},
journal = {IEEE Transactions on Nuclear Science},
volume = {60},
number = {6},
pages = {4362--4367},
month = {12},
year = {2013},
}
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