尾上研究室 研究業績一覧: T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design, December 2006.
  • リスト
  •  表 
  • LaTeX
  • BibTeX
Detail of a work
Tweet
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E89-A(12), pp. 3560-3568, December 2006.
ID 572
分類 論文誌
タグ
表題 (title) Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
表題 (英文)
著者名 (author) T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto
英文著者名 (author)
キー (key)
定期刊行物名 (journal) IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
定期刊行物名 (英文)
巻数 (volume) E89-A
号数 (number) 12
ページ範囲 (pages) 3560-3568
刊行月 (month) 12
出版年 (year) 2006
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル 利用できません.
BiBTeXエントリ
@article{id572,
         title = {Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in SoC Design},
        author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E89-A},
        number = {12},
         pages = {3560-3568},
         month = {12},
          year = {2006},
}
  

Search

Tags

1 件の該当がありました. : このページのURL : HTML

Language: 英語 | 日本語 || ログイン |

This site is maintained by Onoye Lab.
PMAN 3.2.10 build 20181029 - Paper MANagement system / (C) 2002-2016, Osamu Mizuno
Time to show this page: 0.02425 seconds.