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T. Yuasa, A. Tomita, T. Izumi, T. Onoye, and Y. Nakamura, "An Approach for Circuit Size Reduction by Variable Reordering for Pca-Chip2," In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 217--221, April 2003. | |
ID | 380 |
分類 | 国際会議 |
タグ | |
表題 (title) |
An Approach for Circuit Size Reduction by Variable Reordering for Pca-Chip2 |
表題 (英文) |
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著者名 (author) |
T. Yuasa,A. Tomita,T. Izumi,T. Onoye,Y. Nakamura |
英文著者名 (author) |
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編者名 (editor) |
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編者名 (英文) |
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キー (key) |
, , , Takao Onoye, Yasuhisa Nakamura |
書籍・会議録表題 (booktitle) |
Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies |
書籍・会議録表題(英文) |
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巻数 (volume) |
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号数 (number) |
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ページ範囲 (pages) |
217--221 |
組織名 (organization) |
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出版元 (publisher) |
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出版元 (英文) |
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出版社住所 (address) |
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刊行月 (month) |
4 |
出版年 (year) |
2003 |
採択率 (acceptance) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | 利用できません. |
BiBTeXエントリ |
@inproceedings{id380, title = {An approach for circuit size reduction by variable reordering for PCA-chip2}, author = {T. Yuasa and A. Tomita and T. Izumi and T. Onoye and Y. Nakamura}, booktitle = {Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies}, pages = {217--221}, month = {4}, year = {2003}, } |