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| M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, "Code Efficiency Evaluation for Embedded Processors," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, E85-A(4), pp. 811--818, April 2002. | |
| ID | 38 |
| 分類 | 論文誌 |
| タグ | |
| 表題 (title) |
Code Efficiency Evaluation for Embedded Processors |
| 表題 (英文) |
Code Efficiency Evaluation for Embedded Processors |
| 著者名 (author) |
M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, I. Shirakawa |
| 英文著者名 (author) |
M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, I. Shirakawa |
| キー (key) |
Morgan Hirosuke Miki, , , Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa |
| 定期刊行物名 (journal) |
IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences |
| 定期刊行物名 (英文) |
IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences |
| 巻数 (volume) |
E85-A |
| 号数 (number) |
4 |
| ページ範囲 (pages) |
811--818 |
| 刊行月 (month) |
4 |
| 出版年 (year) |
2002 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@article{id38,
title = {Code Efficiency Evaluation for Embedded Processors},
author = {M. H. Miki and M. Sakamoto and S. Miyamoto and Y. Takeuchi and T. Yoshida and I. Shirakawa},
journal = {IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences},
volume = {E85-A},
number = {4},
pages = {811--818},
month = {4},
year = {2002},
}
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