尾上研究室 研究業績一覧: T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design, May 2006.
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T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227--230, May 2006.
ID 359
分類 国際会議
タグ
表題 (title) Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
表題 (英文)
著者名 (author) T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto
英文著者名 (author)
編者名 (editor)
編者名 (英文)
キー (key) Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
書籍・会議録表題 (booktitle) Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)
書籍・会議録表題(英文)
巻数 (volume)
号数 (number)
ページ範囲 (pages) 227--230
組織名 (organization)
出版元 (publisher)
出版元 (英文)
出版社住所 (address)
刊行月 (month) 5
出版年 (year) 2006
採択率 (acceptance)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル 利用できません.
BiBTeXエントリ
@inproceedings{id359,
         title = {Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design},
        author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M. Hashimoto},
     booktitle = {Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)},
         pages = {227--230},
         month = {5},
          year = {2006},
}
  

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