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H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "A Low-Power DSP Core Architecture for Low Bitrate Speech Codec," IEICE Trans. Fundamentals, E81-C(8), pp. 1616--1621, August 1998. | |
ID | 19 |
分類 | 論文誌 |
タグ | |
表題 (title) |
A Low-Power DSP Core Architecture for Low Bitrate Speech Codec |
表題 (英文) |
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著者名 (author) |
H. Okuhata, Morgan H. Miki, T. Onoye, I. Shirakawa |
英文著者名 (author) |
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キー (key) |
Hiroyuki Okuhata, Morgan Hirosuke Miki, Takao Onoye, Isao Shirakawa |
定期刊行物名 (journal) |
IEICE Trans. Fundamentals |
定期刊行物名 (英文) |
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巻数 (volume) |
E81-C |
号数 (number) |
8 |
ページ範囲 (pages) |
1616--1621 |
刊行月 (month) |
8 |
出版年 (year) |
1998 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | 利用できません. |
BiBTeXエントリ |
@article{id19, title = {A Low-Power {DSP} Core Architecture for Low Bitrate Speech Codec}, author = {H. Okuhata and Morgan H. Miki and T. Onoye and I. Shirakawa}, journal = {IEICE Trans. Fundamentals}, volume = {E81-C}, number = {8}, pages = {1616--1621}, month = {8}, year = {1998}, } |