論文誌

[1] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, , Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005.

国際会議

[1] Y. Masuda, M. Hashimoto, and T. Onoye, "Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation," In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 28-35, March 2016.

[2] Y. Masuda, M. Hashimoto, and T. Onoye, "Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise," In Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 315-322, November 2015.

[3] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, "Stochastic Timing Error Rate Estimation under Process and Temporal Variations," In Proceedings of International Test Conference (ITC), October 2015.