論文誌

[1] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Exploring Well-Configurations for Minimizing Single Event Latchup," IEEE Transactions on Nuclear Science, volume 61, number 6, pages 3282--3289, December 2014.

[2] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4362--4367, December 2013.

[3] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in Sram at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4232--4237, December 2013.

国際会議

[1] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 Nm Sram," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.

[2] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 Nm Bulk Cmos," Proceedings of International Reliability Physics Symposium (IRPS), April 2015.

[3] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Optimizing Well-Configuration for Minimizing Single Event Latchup," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.

[4] T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, "Preventing Single Event Latchup with Deep P-Well on P-Substrate," Proceedings of International Reliability Physics Symposium (IRPS), June 2014.

[5] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of Sram and Ff of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk Cmos Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.

[6] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in Sram at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.

[7] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.

[8] R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, "VLSI Architecture of H.264 RDO-BASED Block Size Decision for 1080 HD," In Proc. PCS, November 2007.

[9] R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, "VLSI Architecture of H.264 Block Size Decision Based on Rate-Distortion Optimization," In Proc. ISPACS, pages 618--621, December 2006.