論文誌

[1] T. Enami, T. Sato, and M. Hashimoto, "Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2261--2271, December 2012.

[2] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume 93-A, number 12, pages 2399-2408, December 2010.

[3] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 4, pages 541-553, April 2009.

[4] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Trans. on Circuits and Systems—II: Express Briefs, volume 54, number 10, pages 868-872, October 2007.

国際会議

[1] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 41-46, March 2010.

[2] T. Enami, M. Hashimoto, and T. Sato, "Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis," In Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 420-425, November 2008.

[3] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," In Proc. ACM International Symposium on Physical Design, pages 160-167, April 2008. [1.txt]

[4] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proc.~IEEE Custom Integrated Circuits Conference, pages 861--864, September 2006.

研究会等発表論文

[1] 小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史, 尾上孝雄, "電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法," 信学技報, CPM2006-132, ICD2006-174, pages 19--23, 2007年1月.