論文誌

[1] T. Watanabe and N. Ishiura, "Resister Constraint Analysis to Minimize Spill Code for Application Specific DSPs," IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, volume E84-A, number 6, pages 1541--1544, June 2001.

[2] M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, "Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes," IEICE Trans. Fundamentals, volume E83-A, number 12, pages 2456--2463, December 2000.

[3] M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, volume E80-A, number 10, pages 1853-1860, October 1997.

[4] S. Yano and N. Ishiura, "Embedded Memory Array Testing Using a Scannable Configuration," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, volume E80-A, number 10, pages 1934-1944, October 1997.

[5] S. Yano, K. Akagi, H. Inohara, and N. Ishiura, "Application of Full Scan Design to Embedded Memory Arrays," in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E80-A, number 3, March 1997.

国際会議

[1] T. Watanabe and N. Ishiura, "Minimization of Spill Code Insertion by Register Constraint Analysis for Code Generation for Application Specific DSPs," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 953--956, July 2000.

[2] N. Ishiura, T. Watanabe, and M. Yamaguchi, "A Code Generation Method for Datapath Oriented Application Specific Processor Design," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pages 71--78, April 2000.

[3] M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, "Thread Partitioning Method for Hardware Compiler Bach," In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2000), pages 303--308, January 2000.

[4] N. Ishiura and M. Yamaguchi, "Operation Binding for Retargetable Compilers Minimizing Clock Cycles," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pages 705--708, July 1999.

[5] N. Ishiura, M. Yamaguchi, and T. Kambe, "A Graph-Based Algorithm of Operation Binding for Compilers Targeting Heterogeneous Datapath," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pages 395--398, November 1998.

[6] J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, "Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding," In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pages 141--151, September 1998.

[7] N. Ishiura, M. Yamaguchi, and N. Nitta, "Field Partitioning Algorithms for Compression of Instruction Codes of Application Specific VLIW Processors," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1387--1390, July 1998.

[8] M. Yamaguchi, N. Ishiura, and T. Kambe, "A Binding Algorithm for Retargetable Compilation to Non-Orthogonal Datapath Architectures," In in Proc. International Symposium on Circuits and Systems, WPA4-4, June 1998.

[9] M. Yamaguchi, N. Ishiura, and T. Kambe, "Binding and Scheduling Algorithms for Highly Retargetable Compilation," In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pages 93-98, February 1998.

[10] N. Ishiura and M. Yamaguchi, "Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning," In in Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), pages 105-109, December 1997.

[11] S. Nakamura, N. Ishiura, T. Yamamoto, and I. Shirakawa, "High-Level Synthesis System for Behavioral Descriptions with Conditional Branches," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 935-938, July 1996.

研究会等発表論文

[1] S. Yano, K. Akagi, and N. Ishiura, "A New Scan Path Approach to Memory Array Testing," In 電子情報通信学会第9回回路とシステム軽 井沢ワークショップ, pages 55-60, April 1996.