論文誌

[1] S. Kimura, M. Hashimoto, and T. Onoye, "A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2292--2300, December 2012.

[2] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 4, pages 899-906, April 2005.

[3] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of Java Accelerator for High-Performance Embedded Systems," in IEICE Trans. Fundamentals, volume E86-A, number 12, pages 3079--3088, December 2003.

国際会議

[1] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 283--289, February 2012.

[2] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 46--51, April 2011.

[3] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Embedded Architecture of IEEE802.11i Cipher Algorithms," In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pages 241--246, September 2004.

[4] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "A Java Accelerator for High Performance Embedded Systems," In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.

[5] M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, "High Performance Java Hardware Engine and Software Kernel for Embedded Systems," In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pages 365--369, December 2001.

[6] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "High Performance Java Execution for Embedded Systems," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 346--350, October 2001.