論文誌

[1] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication," J. Circuits, Systems, and Computers, volume 7, number 5, pages 441-457, May 1997.

国際会議

[1] J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, "Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding," In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pages 141--151, September 1998.

[2] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication," In in Proc. IEEE Custom Integrated Circuits Conference, pages 229-232, May 1997.

[3] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pages 480-483, November 1996.

[4] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "Implementation of Very Low Bitrate Video Encoder Core," In in Proc. 2nd International Conference on ASIC, pages 131-134, October 1996.

[5] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Architecture for Very Low Bitrate Video Encoder Core," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 294-297, July 1996.