論文誌

[1] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014.

国際会議

[1] R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.

[2] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi Author(s) in English , "A Novel Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch (2v-1cas) for Nonvolatile Crossbar Switch with Multiple Fan-Outs," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pages 32--35, December 2015.

[3] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015.

[4] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313-316, November 2013.

[5] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient Vlsi Architecture for Signal Processing," In Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009.

[6] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 186--192, August 2009.

[7] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability," In Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.

[8] H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and Y. Nakamura, "Efficient Memory Architecture for JPEG2000 Entropy Codec," In Proc. International Symposium on Circuits and Systems, pages 2881--2884, May 2006.