論文誌

[1] G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa, "Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation," In IEICE Trans. Fundamentals, volume E89-A, number 4, pages 941--949, April 2006.

[2] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection by Digital Watermarking for MPEG-4 Video Coding," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 6, pages 1281--1288, June 2002.

[3] G. Fujita, T. Onoye, and I. Shirakawa, "A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding," IEICE Trans. Electronics, volume E81-C, number 5, pages 702--707, May 1998.

[4] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication," J. Circuits, Systems, and Computers, volume 7, number 5, pages 441-457, May 1997.

[5] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai, "Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL," in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E79-A, number 8, pages 1210-1216, August 1996.

国際会議

[1] K. Watanabe, G. Fujita, T. Homemoto, and R. Hashimoto, "A High-Speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator," The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pages 6-10, March 2012.

[2] Huynh Van Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Real-Time Human Object Extraction for Mobile Terminal," In in Proc.The 20th Commemorative International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005), Jeju, Korea, volume 3, pages 1015-1016, July 2005.

[3] T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, "Embedded System Implementation of Scalable and Object-Based Video Coding," In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.

[4] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Modified Snake: Real-Time Face Object Extraction for Video Phone," In in Proc. IEEE International Conference on Image Processing(ICIP2003), Barcelona, Spain, volume III, pages 873--876, September 2003.

[5] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Efficient Error Recovery Scheme for MPEG-4 Video Coding," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 2, pages 1328--1331, July 2003.

[6] T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa, "Vlsi Architecture for Mpeg-4 Core Profile Codec Core," In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pages 365--371, April 2003.

[7] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Realtime Face Object Extraction Algorithm for Video Phone," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), Orchard Road, Singapore, volume 1, pages 35--38, December 2002.

[8] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Digital Watermark Based Error Detection for MPEG-4 Bitstream Error," In ibid, pages 152--155, July 2002.

[9] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Hybrid Error Concealment Algorithm for MPEG-4 Videodecoders," In ibid, pages 611--614, July 2002.

[10] H. Okada, H. S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection Based on Check Marker Embedding for MPEG-4 Video Coding," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 96--99, July 2001.

[11] H. S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Error Concealment Algorithm by Motion Estimation Method for MPEG-4 Video Decoder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 104--107, July 2001.

[12] T. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Low Power Architecture for H.263 Version2 Codec," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 620--623, July 2001.

[13] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "Realtime Wavelet Video Coder Based on Reduced Memory Accessing," In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pages 15--16, January 2001.

[14] R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa, "Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 811--814, July 2000.

[15] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of a Realtime Wavelet Video Coder," In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pages 543--546, May 2000.

[16] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Video Coding Algorithm Based on Modified Discrete Wavelet Transform," In in Proc. NOLTA'99, volume I, pages 251--254, November 1999.

[17] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Architecture of Embedded Zerotree Wavelet Based Real-Time Video Coder," In in Proc. 12th IEEE ASIC/SOC Conference, pages 137-141, October 1999.

[18] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Embedded Zerotree Wavelet Based Algorithm for Video Compression," In in Proc. IEEE Region 10 Conference (TENCON '99), pp.II-1343--1346, September 1999.

[19] M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, "Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, volume IV, pages 572--575, June 1999.

[20] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Low-Power Architecture of H.324 Codec Dedicated to Mobile Computing," In in Proc. EUROMEDIA'99 , Munich, Germany, pages 145--149, April 1999.

[21] J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, "Structual Objeco-Oriented Video Segmentation and Representation Algorithm," In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pages 78--82, November 1998.

[22] J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, "Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding," In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pages 141--151, September 1998.

[23] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, "A Wireless Data System Constructed of SAW-Based Receiver/Transmitter and Its Applications to Medical Cares," In in Proc. IEEE Radio & Wireless Conf., pages 47--50, August 1998.

[24] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Implementation of DWT and EZW Cores for a Bitrate Scalable Video Coder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 221--224, July 1998.

[25] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, "A Wireless Data System by Means of SAW-Based Transmitter/Receiver and Its Applications to Medical Cares," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 299--302, July 1998.

[26] D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, "VLSI Implementation of a Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1383--1386, July 1998.

[27] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, "A Wireless Data Systems Constructed of SAW-Divices and Its Applications to Medical Cares," In in Proc. Analog VLSI WS, pages 39--44, June 1998.

[28] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of H.324 Audiovisual Codec for Mobile Computing," In in Proc. IEEE Custom Integrated Circuits Conference, pages 193--196, May 1998.

[29] T. Onoye, G. Fujita, H. Okuhata, M. H. Miki, and I. Shirakawa, "Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing," In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pages 589-594, February 1998.

[30] M. H. Miki, G.Fujita, T. Onoye, and I. Sirakawa, "Low-Power H.263 Video CoDec Dedicated to Mobile Computing," In in Proc. International Symposium on Low Power Electronics and Design, pages 80-83, August 1997.

[31] G. Fujita, T. Onoye, and I. Sirakawa, "A New Motion Estimation Core Dedicated to H.263 VideoCoding," In in Proc. IEEE International Symposium on Circuits and Systems, pages 1161-1164, June 1997.

[32] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication," In in Proc. IEEE Custom Integrated Circuits Conference, pages 229-232, May 1997.

[33] G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura, "Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@HL," In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pages 949-954, November 1996.

[34] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pages 480-483, November 1996.

[35] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "Implementation of Very Low Bitrate Video Encoder Core," In in Proc. 2nd International Conference on ASIC, pages 131-134, October 1996.

[36] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura, "A Single Chip Motion Estimator Dedicated to MPEG2 MP@HL," In in Proc. European Signal Processing Conference, pages 1479-1482, September 1996.

[37] G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa, "Single Chip MPEG2 MP@ML Motion Estimator," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 286-289, July 1996.

[38] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Architecture for Very Low Bitrate Video Encoder Core," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 294-297, July 1996.

[39] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@HL," In in Proc. IEEE Custom Integrated Circuits Conference, pages 351-354, May 1996.

[40] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "A VLSI Architecture of MPEG2 MP@HL Motion Estimator," In in Proc. IEEE Int'l Symposium on Circuits and Systems, pages 664-667, May 1996.