論文誌

[1] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic," Trans. of IPSJ, volume 41, number 4, pages 899--907, April 2000.

[2] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power Scheme of NMOS 4-Phase Dynamic Logic," IEICE Trans. Electron., volume E82--C, number 9, pages 1772--1776, September 1999.

国際会議

[1] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic," In in Proc. ASP-DAC2000, pages 529--532, January 2000.

[2] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array," In in Proc. IEEE Region 10 Conference (TENCON '99), pages 872--875, September 1999.

[3] B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pages 561--564, July 1999.

[4] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power Implementation by a New Logic Scheme of NMOS 4-Phase Dynamic Logic," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pages 235--240, October 1998.

[5] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Delay and Power Simulation for a New Logic Scheme of NMOS 4-Phase Dynamic Logic," In in Proc. European Simulation Symposium, pages 339--343, October 1998.

[6] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "An Object Code Compression Approach to Embedded Processors," In in Proc. International Symposium on Low Power Electronics and Design, pages 265-268, August 1997.

[7] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "Low-Power Consumption Architecture for Embedded Processor," In in Proc. 2nd International Conference on ASIC, pages 77-80, October 1996.