|
著者名 (author) |
表題 (title) |
論文誌/会議名 |
巻数 (volume) |
号数 (number) |
ページ範囲 (pages) |
刊行月 (month) |
出版年 (year) |
IF / Acc. rate |
File |
論文誌
|
H. Fuketa, R. Harada, M. Hashimoto, T. Onoye
|
Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM
|
IEEE Transactions on Device and Materials Reliability
|
|
|
|
|
(to appear)
|
|  |
論文誌
|
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
|
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
IEEE Transactions on Nuclear Science
| 59
|
6
|
2791--2795
|
December
|
2012
|
| |
論文誌
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
|
IEEE Transactions on VLSI Systems
| 20
|
2
|
333--343
|
February
|
2012
|
| |
論文誌
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
IEEE Transactions on Nuclear Science
| 58
|
4
|
2097--2102
|
August
|
2011
|
| |
論文誌
|
H. Fuketa, D. Kuroda, M. Hashimoto, T. Onoye
|
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion
|
IEEE Transactions on Circuits and Systems II
| 58
|
5
|
299--303
|
May
|
2011
|
| |
論文誌
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Transistor Variability Modeling and Its Validation with Ring-oscillation Frequencies for Body-biased Subthreshold Circuits
|
IEEE Transactions on VLSI Systems
| 18
|
7
|
1118--1129
|
July
|
2010
|
| |
論文誌
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Trade-off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E92-A
|
12
|
3094--3102
|
December
|
2009
|
| |
論文誌
|
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
|
IEICE Trans. on Electronics
| E92-C
|
2
|
281--285
|
February
|
2009
|
| |
国際会議
|
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
|
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
|
July
|
2012
|
|
|
国際会議
|
M. Hashimoto, H. Fuketa
|
Adaptive Performance Compensation with On-Chip Variation Monitoring (invited)
|
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)
|
|
|
|
August
|
2011
|
| |
国際会議
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
213--217
|
May
|
2010
|
|  |
国際会議
|
D. Kuroda, H. Fuketa, M. Hashimoto, T. Onoye
|
A 16-bit RISC Processor with 4.18pJ/cycle at 0.5V Operation
|
Proceedings of IEEE COOL Chips
|
|
|
190
|
April
|
2010
|
| |
国際会議
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
|
361 -- 362
|
January
|
2010
|
| |
国際会議
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
|
215--218
|
September
|
2009
|
| |
国際会議
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Trade-off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
|
266-271
|
January
|
2009
|
| |
国際会議
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-biased Circuits and Subthreshold Circuits
|
Proceedings of Workshop on Test Structure Design for Variability Characterization
|
|
|
|
November
|
2008
|
|
|
国際会議
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits
|
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
|
|
|
3--8
|
August
|
2008
|
| |
国際会議
|
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --
|
Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI)
|
|
|
387--390
|
May
|
2008
|
| |
国際会議
|
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
A study on body-biasing layout style focusing on area efficiency and speed
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
|
233-237
|
October
|
2007
|
|
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