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論文誌
[1]  D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, (to appear).
[2]  T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,'' IEICE Trans. on Information and Systems , (to appear).
[3]  I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, ``A 0.8-V 110-Na Cmos Current Reference Circuit Using Subthreshold Operation,'' IEICE Electronics Express (ELEX), vol. 10, no. 4, March 2013.
[4]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 2, pp. 459--468, February 2013.
[5]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating Nbti-Induced Delay Degradation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 12, pp. 2545--2553, December 2011.
[6]  H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, and M. Hashimoto, ``Proposal of Metrics for Ssta Accuracy Evaluation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 4, pp. 808--814, April 2007.
[7]  T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M Hashimoto, ``Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3666-3670, December 2006.
[8]  金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜, ``遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法,'' 情報処理学会論文誌, vol. 44, no. 5, pp. 1301-1310, May 2003.
国際会議
[1]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Converter Based on Minimax Sampling,'' Proceedings of International SoC Design Conference (ISOCC), p. 120 -- 123 , November 2012.
[2]  T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.
[3]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , pp. 189--194, September 2011.
[4]  T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Nbti Mitigation by Giving Random Scan-In Vectors during Standby Mode,'' Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pp. 152--161, September 2011.
[5]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.
[6]  D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability,'' IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.
[7]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 646--651, March 2010.
[8]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Soft Error Resilient Vlsi Architecture for Signal Processing,'' Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 183--186, December 2009.
[9]  D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.
[10]  Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 236--241, March 2009.
[11]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability,'' Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
[12]  T. Kouno, M. Hashimoto, and H. Onodera, ``Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 453-456, November 2005.
[13]  T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, and M. Hashimoto, ``Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149-155, January 2003.
[14]  T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, and H. Onodera, ``Vector Quantization Processor for Mobile Video Communication,'' In Proceedings of IEEE International ASIC/SOC Conference, pp. 75-79, September 2000.
国内会議(査読付き)
[1]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax,'' 電子情報通信学会 集積回路研究会, no. ICD2011-121, pp. 105--107, December 2011.
[2]  小林宏行、小野信任、佐藤高史、岩井二郎、橋本昌宜, ``統計的STA の精度検証手法,'' 情報処理学会DAシンポジウム, pp. 7-12, July 2006.
[3]  小林 宏行, 小野 信任, 佐藤 高史, 岩井 二郎, 橋本 昌宜, ``統計的STAの有効性の検証手法,'' 第19回 回路とシステム(軽井沢)ワークショップ, pp. 553-558, April 2006.
[4]  金本 俊幾, 阿久津滋聖, 中林 太美世, 一宮 敬弘, 蜂屋 孝太郎, 石川 博, 室本 栄, 小林 宏行, 橋本 昌宜, 黒川 敦, ``遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価,'' 情報処理学会DAシンポジウム, pp. 265-270, July 2004.
[5]  佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, ``インダクタンスに起因する配線遅延変動の統計的予測手法,'' 2002年電子情報通信学会ソサイエティ大会講演論文集, no. TA-2-4, pp. 247-248, September 2002.
[6]  金本 俊幾, 佐藤 高史, 黒川 敦, 川上 善之, 岡 宏規, 北浦 智靖, 池内 敦彦, 小林 宏行, 橋本 昌宜, ``0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法,'' 情報処理学会DAシンポジウム, pp. 149-154, July 2002.
[7]  佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, ``インダクタンスが配線遅延に及ぼす影響の定量的評価方法,'' 第15回 回路とシステム(軽井沢)ワークショップ, pp. 493-498, April 2002.

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