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論文誌
[1]  D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, (to appear).
[2]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of Nbti-Induced Pulse-Width Modulation on Set Pulse-Width Measurement,'' IEEE Transactions on Nuclear Science, (to appear).
[3]  K. Shinkai, M. Hashimoto, and T. Onoye, ``A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations,'' Integration, the VLSI Journal, (to appear).
[4]  H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10t Subthreshold Sram,'' IEEE Transactions on Device and Materials Reliability, (to appear).
[5]  T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,'' IEICE Trans. on Information and Systems , (to appear).
[6]  Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Supply Noise Suppression by Triple-Well Structure,'' IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp. 781--785, April 2013.
[7]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices,'' IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
[8]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 3, pp. 684--696, March 2013.
[9]  I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, ``A 0.8-V 110-Na Cmos Current Reference Circuit Using Subthreshold Operation,'' IEICE Electronics Express (ELEX), vol. 10, no. 4, March 2013.
[10]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 2, pp. 459--468, February 2013.
[11]  Y. Takai, M. Hashimoto, and T. Onoye, ``Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2220--2225, December 2012.
[12]  S. Kimura, M. Hashimoto, and T. Onoye, ``A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2292--2300, December 2012.
[13]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 20, no. 2, pp. 333--343, February 2012.
[14]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating Nbti-Induced Delay Degradation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 12, pp. 2545--2553, December 2011.
[15]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Extracting Device-Parameter Variations with Ro-Based Sensors,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 12, pp. 2537--2544, December 2011.
[16]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Transactions on Nuclear Science, vol. 58, no. 4, pp. 2097--2102, August 2011.
[17]  H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, ``An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion,'' IEEE Transactions on Circuits and Systems II, vol. 58, no. 5, pp. 299--303, May 2011.
[18]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring Set Pulse Width Distribution with Sub-Fo1-Inverter-Delay Resolution,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2417--2423, December 2010.
[19]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 18, no. 7, pp. 1118--1129, July 2010.
[20]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Prediction of Self-Heating in Short Intra-Block Wires,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 3, pp. 583--594, March 2010.
[21]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3094--3102, December 2009.
[22]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform,'' IEEE Journal of Solid-State Circuits, vol. 44, no. 6, pp. 1745--1755, June 2009.
[23]  T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, ``Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. 92-A, no. 4, pp. 990--997, April 2009.
[24]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Trans. on Electronics, vol. E92-C, no. 2, pp. 281--285, February 2009.
[25]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3481-3487, December 2008.
[26]  Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, ``Area-Efficient Reconfigurable Architecture for Media Processing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3651-3662, December 2008.
[27]  M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' IEICE Trans. on Information and Systems , vol. E91-D, no. 3, pp. 655--660, March 2008.
[28]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects,'' IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718--728, March 2008.
[29]  M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2661-2668, December 2007.
[30]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Trans. on CAS-II, vol. 54, no. 10, pp. 868--872, October 2007.
[31]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling,'' IEICE Trans. on Electronics, vol. E90-C, no. 6, pp. 1267-1273, June 2007.
[32]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 4, pp. 724--731, April 2007.
[33]  H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, and M. Hashimoto, ``Proposal of Metrics for Ssta Accuracy Evaluation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 4, pp. 808--814, April 2007.
[34]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Interconnect Rl Extraction Based on Transfer Characteristics of Transmission-Line,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3585-3593, December 2006.
[35]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[36]  T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3491-3499, December 2006.
[37]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. pp.3375-3381, December 2005.
[38]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3564-3572, December 2005.
[39]  T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment for Minimizing Supply Voltage Drop,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A,, no. 12, pp. 3429-3436, December 2005.
[40]  T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3382-3389, December 2005.
[41]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp. 885-891, April 2005.
[42]  T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' IEICE Trans. on Electronics, vol. E88-C, no. 3, pp. 437-444, March 2005.
[43]  M. Hashimoto and H. Onodera, ``Crosstalk Noise Optimization by Post-Layout Transistor Sizing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E87-A, no. 12, pp. 3251-3257, December 2004.
[44]  M. Hashimoto, Y. Yamada, and H. Onodera, ``Equivalent Waveform Propagation for Static Timing Analysis,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 23, no. 4, pp. 498-508, April 2004.
[45]  M. Hashimoto, M. Takahashi, and H. Onodera, ``Crosstalk Noise Estimation for Generic Rc Trees,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 12, pp. 2965-2973, December 2003.
[46]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Representative Frequency for Interconnect R(F)L(F)C Extraction,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 12, pp. 2942-2951, December 2003.
[47]  M. Hashimoto, Y. Hayashi, and H. Onodera, ``Experimental Study on Cell-Base High-Performance Datapath Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 12, pp. 3204-3207, December 2003.
[48]  M. Hashimoto and H. Onodera, ``Increase in Delay Uncertainty by Performance Optimization,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 12, pp. 2799-2802, December 2002.
[49]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``VLSI 配線の伝送線路特性を考慮した駆動力決定手法,'' 情報処理学会論文誌, vol. 43, no. 5, pp. 1338--1347, May 2002.
[50]  M. Hashimoto and H. Onodera, ``Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E84-A, no. 11, pp. 2769-2777, November 2001.
[51]  M. Hashimoto and H. Onodera, ``A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E83-A, no. 12, pp. 2558-2568, December 2000.
[52]  橋本 昌宜, 小野寺 秀俊, 田丸 啓吉, ``グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法,'' 情報処理学会論文誌, vol. 40, no. 4, pp. 1707-1716, April 1999.
[53]  M. Hashimoto, H. Onodera, and K. Tamaru, ``A Power and Delay Optimization Method Using Input Reordering in Cell-Based Cmos Circuits,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E82-A, no. 1, pp. 159-166, January 1999.
国際会議
[1]  M. Ueno, M. Hashimoto, and T. Onoye, ``Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures,'' Proceedings of Reconfigurable Architectures Workshop (RAW), (to appear).
[2]  T. Shinada, M. Hashimoto, and T. Onoye, ``Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes,'' Proceedings of International NEWCAS Conference, (to appear).
[3]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices,'' Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012.
[4]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Converter Based on Minimax Sampling,'' Proceedings of International SoC Design Conference (ISOCC), p. 120 -- 123 , November 2012.
[5]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of Nbti-­Induced Pulse-Width Modulation on Set Pulse-Width Measurement,'' Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.
[6]  T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.
[7]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2012.
[8]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 283--289, February 2012.
[9]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , pp. 189--194, September 2011.
[10]  Y. Takai, M. Hashimoto, and T. Onoye, ``Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure,'' Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2011.
[11]  T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Nbti Mitigation by Giving Random Scan-In Vectors during Standby Mode,'' Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pp. 152--161, September 2011.
[12]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.
[13]  T. Amaki, M. Hashimoto, and T. Onoye, ``An Oscillator-Based True Random Number Generator with Jitter Amplifier,'' Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 725--728, May 2011.
[14]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing,'' Proceedings of International Reliability Physics Symposium (IRPS), pp. 253--257, April 2011.
[15]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 46--51, April 2011.
[16]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Extracting Device-Parameter Variations with Ro-Based Sensors,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 13--18, March 2011.
[17]  D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability,'' IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.
[18]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 81--82, January 2011.
[19]  Y. Takai, M. Hashimoto, and T. Onoye, ``Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation,'' Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 213--216, October 2010.
[20]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling,'' Proceedings of International Workshop on Information Security Applications (WISA), pp. 107-121, August 2010.
[21]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' Proceedings of International Reliability Physics Symposium (IRPS), pp. 213--217, May 2010.
[22]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' ACM Great Lake Symposium on VLSI (GLSVLSI), pp. 197--202, May 2010.
[23]  Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to Sso,'' Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pp. 19--20, May 2010.
[24]  D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, ``A 16-Bit Risc Processor with 4.18pj/Cycle at 0.5v Operation,'' Proceedings of IEEE COOL Chips, p. 190, April 2010.
[25]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 646--651, March 2010.
[26]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring Set Pulse Width Distribution with Sub-Fo1-Inverter-Delay Resolution,'' Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 839--844, March 2010.
[27]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 89--94, March 2010.
[28]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), p. 361 -- 362, January 2010.
[29]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Soft Error Resilient Vlsi Architecture for Signal Processing,'' Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 183--186, December 2009.
[30]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits,'' Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 215--218, September 2009.
[31]  K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits,'' Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 51--56, August 2009.
[32]  D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.
[33]  Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 236--241, March 2009.
[34]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability,'' Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
[35]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 266-271, January 2009.
[36]  Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process,'' Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 397--400, November 2008.
[37]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits,'' Proceedings of Workshop on Test Structure Design for Variability Characterization, November 2008.
[38]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits,'' Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 3--8, August 2008.
[39]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --,'' Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI), pp. 387--390, May 2008.
[40]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 520--525, March 2008.
[41]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 107--108, January 2008.
[42]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed,'' Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 233-237, October 2007.
[43]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect,'' Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 783--786, September 2007.
[44]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Future Prediction of Self-Heating in Short Intra-Block Wires,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 660-665, March 2007.
[45]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 47-53, November 2006.
[46]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects,'' In Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 70-75, October 2006.
[47]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 721-724, September 2006.
[48]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC),, pp. 861-864, September 2006.
[49]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227-230, May 2006.
[50]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations,'' In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 59-64, February 2006.
[51]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Interconnect Rl Extraction at a Single Representative Frequency,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 515-520, January 2006.
[52]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction,'' In Proceedings of International Workshop on Compact Modeling (IWCM), pp. 51-56, January 2006.
[53]  T. Kouno, M. Hashimoto, and H. Onodera, ``Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 453-456, November 2005.
[54]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip High-Throughput Global Signaling,'' In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 79-82, October 2005.
[55]  S. Uemura, T. Miyazaki, M. Hashimoto, and H. Onodera, ``Estimation of Maximum Oscillation Frequency for Cmos Lcvcos,'' In Proceedings of IEEJ International Analog VLSI Workshop, October 2005.
[56]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Delay Variation Due to Inductive Coupling,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 305-308, September 2005.
[57]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 613-616, September 2005.
[58]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pp. 201-202, May 2005.
[59]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics,'' In Proceedings of International Meeting for Future of Electron Devices, Kansai, pp. 33-34, April 2005.
[60]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' In Proceedings of International Symposium on Physical Design (ISPD), pp. 63-69, April 2005.
[61]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 402-407, March 2005.
[62]  T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 723-728, January 2005.
[63]  M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1098-1101, January 2005.
[64]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Return Path Selection for Loop Rl Extraction,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1078-1081, January 2005.
[65]  T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1074-1077, January 2005.
[66]  A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um Cmos Process,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), p. D9-D10, January 2005.
[67]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip Global Signaling,'' In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) , pp. 87-100, November 2004. (Invited talk)
[68]  M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 814-820, November 2004.
[69]  M. Hashimoto, A. Tsuchiya, and H. Onodera, ``On-Chip Global Signaling by Wave Pipelining,'' In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 311-314, October 2004.
[70]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Lsi Power Network Analysis with On-Chip Wire Inductance,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 55-60, October 2004.
[71]  T. Sato, M. Hashimoto, and H. Onodera, ``An Ir-Drop Minimization by Optimizing Number and Location of Power Supply Pads,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 66-72, October 2004.
[72]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 214-219, October 2004.
[73]  T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' In IEEJ International Analog VLSI Workshop, pp. 45-50, October 2004.
[74]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 489-492, September 2004.
[75]  A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Optimization of Cmos Current Mode Logic Dividers,'' In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits , pp. 434-435, August 2004.
[76]  M. Hashimoto, K. Fujimori, and H. Onodera, ``Automatic Generation of Standard Cell Library in Vdsm Technologies,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 36-41, March 2004.
[77]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Representative Frequency for Interconnect R(F)L(F)C Extraction,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 691-696, January 2004.
[78]  T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Comparison of Plls for Clock Generation Using Ring Oscillator Vco and Lc Oscillator in a Digital Cmos Process,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 545-546, January 2004.
[79]  M. Hashimoto, Y. Yamada, and H. Onodera, ``Equivalent Waveform Propagation for Static Timing Analysis,'' In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 169-175, November 2003.
[80]  M. Hashimoto, Y. Yamada, and H. Onodera, ``Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis,'' In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pp. 18-23, April 2003.
[81]  Y. Yamada, M. Hashimoto, and H. Onodera, ``Slew Calculation Against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 280-287, April 2003.
[82]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Frequency Determination for Interconnect Rlc Extraction,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 288-293, April 2003.
[83]  M. Hashimoto, K. Fujimori, and H. Onodera, ``Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 589-590, January 2003.
[84]  M. Hashimoto, D. Hiramatsu, A. Tsuchiya, and H. Onodera, ``Interconnect Structures for High-Speed Long-Distance Signal Transmission,'' In Proceedings of IEEE International ASIC/SOC Conference, pp. 426-430, September 2002.
[85]  M. Hashimoto, Y. Hayashi, and H. Onodera, ``Experimental Study on Cell-Base High-Performance Datapath Design,'' In Proceedings of IEEE/ACM International Workshop on Logic & Synthesis (IWLS), pp. 283-287, June 2002.
[86]  M. Hashimoto, M. Takahashi, and H. Onodera, ``Crosstalk Noise Optimization by Post-Layout Transistor Sizing,'' In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pp. 126-130, April 2002.
[87]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 377-381, October 2001.
[88]  M. Takahashi, M. Hashimoto, and H. Onodera, ``Crosstalk Noise Estimation for Generic Rc Trees,'' In Proceedings of International Conference on Computer Design (ICCD), pp. 110-116, September 2001.
[89]  H. Onodera, M. Hashimoto, and T. Hashimoto, ``Asic Design Methodology with On-Demand Library Generation,'' In Proceedings of Symposium on VLSI Circuits, pp. 57-60, June 2001.
[90]  M. Hashimoto and H. Onodera, ``Increase in Delay Uncertainty by Performance Optimization,'' In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), vol. V, pp. 379-382, May 2001.
[91]  M. Hashimoto and H. Onodera, ``Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 359-365, January 2001.
[92]  M. Hashimoto and H. Onodera, ``A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing,'' In Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 34-37, December 2000.
[93]  T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, and H. Onodera, ``Vector Quantization Processor for Mobile Video Communication,'' In Proceedings of IEEE International ASIC/SOC Conference, pp. 75-79, September 2000.
[94]  M. Hashimoto and H. Onodera, ``A Performance Optimization Method by Gate Sizing Using Statistical Static Timing Analysis,'' In Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 111-116, April 2000.
[95]  M. Hashimoto and H. Onodera, ``A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis,'' In Proceedings of the Ninth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 115-121, April 2000.
[96]  M. Hashimoto, H. Onodera, and K. Tamaru, ``Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design,'' In Proceedings of the 36th IEEE/ACM Design Automation Conference (DAC), pp. 446-451, January 1999.
[97]  M. Hashimoto, H. Onodera, and K. Tamaru, ``A Power Optimization Method Considering Glitch Reduction by Gate Sizing,'' In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 221-226, August 1998.
[98]  M. Hashimoto, H. Onodera, and K. Tamaru, ``Input Reordering for Power and Delay Optimization,'' In Proceedings of IEEE International ASIC Conference and Exhibit, pp. 194-198, September 1997.
国内会議(査読付き)
[1]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax,'' 電子情報通信学会 集積回路研究会, no. ICD2011-121, pp. 105--107, December 2011.
[2]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測,'' 電子情報通信学会 集積回路研究会, no. ICD2006-173, January 2007.
[3]  小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史、尾上 孝雄, ``電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現,'' 電子情報通信学会 集積回路研究会,, no. ICD2006-174, January 2007.
[4]  Jangsombatsiri Siriporn, 橋本 昌宜, 尾上 孝雄, ``シャントコンダクタンスを挿入したオンチップ伝送線路特性評価,'' 第十回シリコンアナログRF研究会, November 2006.
[5]  新開 健一, 橋本 昌宜, 尾上 孝雄, ``短距離ブロック内配線の自己発熱問題の将来予測,'' 2006年電子情報通信学会ソサイエティ大会講演論文集, no. A-3-14, September 2006.
[6]  榎並孝司、橋本昌宜、尾上孝雄, ``主成分分析による電源電圧変動の統計的モデル化手法,'' 情報処理学会DAシンポジウム, pp. 205-210, July 2006.
[7]  小林宏行、小野信任、佐藤高史、岩井二郎、橋本昌宜, ``統計的STA の精度検証手法,'' 情報処理学会DAシンポジウム, pp. 7-12, July 2006.
[8]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測,'' 第19回 回路とシステム(軽井沢)ワークショップ, pp. 5-10, April 2006.
[9]  新開 健一, 橋本 昌宜, 黒川 敦, 尾上 孝雄, ``電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル,'' 第19回 回路とシステム(軽井沢)ワークショップ, pp. 559-564, April 2006.
[10]  小林 宏行, 小野 信任, 佐藤 高史, 岩井 二郎, 橋本 昌宜, ``統計的STAの有効性の検証手法,'' 第19回 回路とシステム(軽井沢)ワークショップ, pp. 553-558, April 2006.
[11]  榎並 孝司, 橋本 昌宜, 尾上 孝雄, ``電源ノイズ解析のための回路動作部表現法の評価,'' 2006年電子情報通信学会総合大会講演論文集, no. A-3-15, March 2006.
[12]  上村 晋一朗, 土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``ロードマップに準拠したSPICEトランジスタモデルの構築,'' 2006年電子情報通信学会総合大会講演論文集, no. A-3-16, March 2006.
[13]  土谷 亮, 新名 亮規, 橋本 昌宜、小野寺 秀俊, ``CMLを用いたオンチップ長距離高速信号伝送技術の開発,'' 第9回システムLSIワークショップ, pp. 275-278, November 2005.
[14]  上村 晋一朗, 橋本 昌宜, 小野寺 秀俊, ``LC共振器におけるMOSFETの抵抗成分を考慮した等価並列抵抗の見積もり,'' 2005年電子情報通信学会ソサイエティ大会講演論文集, no. C-12-39, September 2005.
[15]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``配線の伝達特性ﾉ基づく抽出周波数決定手法,'' 情報処理学会DAシンポジウム, pp. 169-174, August 2005.
[16]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``誘導性・容量性クロストークノイズによる遅延変動の測定と評価,'' 電子情報通信学会 集積回路研究会, no. ICD2005-74, August 2005.
[17]  上村 晋一朗, 橋本 昌宜, 小野寺 秀俊, ``SOIの基板抵抗率がLNAの性能に及ぼす影響の評価,'' 第四回シリコンアナログRF研究会, May 2005.
[18]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``オンチップ高速信号伝送における終端抵抗決定手法,'' 第18回 回路とシステム(軽井沢)ワークショップ, pp. 425-430, April 2005.
[19]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``オンチップ高速信号伝送用配線の解析的性能評価,'' 電子情報通信学会 VLSI設計技術研究会, no. VLD2004-145, March 2005.
[20]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``実測と電磁界解析による基板損失の評価,'' 第三回シリコンアナログRF研究会, January 2005.
[21]  上村 晋一朗, 橋本 昌宜, 小野寺 秀俊, ``LC型VCO最大発振周波数の実験的検討,'' 第三回シリコンアナログRF研究会, January 2005.
[22]  橋本 昌宜, 小野寺 秀俊, ``微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応--,'' 2004年電子情報通信学会ソサイエティ大会講演論文集, September 2004.
[23]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``基板および周辺信号配線が配線特性に及ぼす影響の実測,'' 第二回シリコンアナログRF研究会, August 2004.
[24]  上村 晋一朗, 橋本 昌宜, 小野寺 秀俊, ``高周波CMOSデバイスモデルを用いたLCVCOの特性見積もりと実測,'' 第二回シリコンアナログRF研究会, August 2004.
[25]  村松 篤, 橋本 昌宜, 小野寺 秀俊, ``オンチップインダクタンスを考慮したLSI電源配線網解析,'' 情報処理学会DAシンポジウム, pp. 277-282, July 2004.
[26]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``配線RL抽出におけるリターンパス選択手法,'' 情報処理学会DAシンポジウム, pp. 175-180, July 2004.
[27]  佐藤 高史, 市宮 淳次, 小野 信任, 蜂屋 孝太郎, 橋本 昌宜, ``フロアプランにおけるオンチップ熱ばらつきの解析と対策,'' 情報処理学会DAシンポジウム, pp. 133-138, July 2004.
[28]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---,'' 第17回 回路とシステム(軽井沢)ワークショップ, pp. 567-572, April 2004.
[29]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響,'' 第一回シリコンアナログRF研究会, April 2004.
[30]  村松 篤, 橋本 昌宜, 小野寺 秀俊, ``電源電圧変動に対するオンチップ配線インダクタンスの影響,'' 2004年電子情報通信学会総合大会講演論文集, no. A-3-22, March 2004.
[31]  山口 隼司, 橋本 昌宜, 小野寺 秀俊, ``ゲート毎の電源電圧変動を考慮した静的遅延解析法,'' 電子情報通信学会 VLSI設計技術研究会, no. ICD2003-236/VLD2003-143, March 2004.
[32]  村松 篤, 橋本 昌宜, 小野寺 秀俊, ``電源配線の等価回路簡略化による電源解析高速化の検討,'' 平成15年度情報処理学会関西支部支部大会 VLSI研究会, no. C-01, pp. 169-172, November 2003.
[33]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``オンチップ高速信号配線における波形歪みの影響,'' 2003年電子情報通信学会ソサイエティ大会講演論文集, no. A-3-6, p. 56, September 2003.
[34]  宮崎 崇仁, 橋本 昌宜, 小野寺 秀俊, ``デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 ーLC発振型VCOを用いたPLLの有効性ー,'' 電子情報通信学会集積回路研究会, no. ICD2003-99, pp. 29-34, September 2003.
[35]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``直交配線を持つオンチップ伝送線路の特性評価,'' 情報処理学会DAシンポジウム, pp. 133-138, July 2003.
[36]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``配線R(f)L(f)C抽出のための代表周波数決定手法,'' 第16回 回路とシステム(軽井沢)ワークショップ, pp. 61-66, April 2003.
[37]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``信号配線と下層配線との結合に対する直交配線の影響,'' 2003年電子情報通信学会総合大会講演論文集, no. A-3-14, p. 81, March 2003.
[38]  宮崎 崇仁, 新名 亮規, 橋本 昌宜, 小野寺 秀俊, ``オンチップオシロ用サンプルホールド回路の広周波数帯域化,'' 2003年電子情報通信学会総合大会講演論文集, no. C-12-34, p. 103, March 2003.
[39]  村松 篤, 橋本 昌宜, 小野寺 秀俊, ``オンチップデカップリング容量の最適寄生抵抗値の決定法,'' 2003年電子情報通信学会総合大会講演論文集, no. A-3-13, p. 80, March 2003.
[40]  山田 祐嗣, 橋本 昌宜, 小野寺 秀俊, ``静的遅延解析のための等価ゲート入力波形導出法　--VDSMプロセスに起因する波形歪みへの対応--,'' 情報処理学会システムLSI設計技術研究会, no. 2003-SLDM-108-20, pp. 111-116, January 2003.
[41]  山田 祐嗣, 橋本 昌宜, 小野寺 秀俊, ``容量性クロストークを考慮した高精度タイミング解析に関する研究,'' 平成14年度情報処理学会関西支部支部大会 VLSI研究会, no. C-3, pp. 113-114, November 2002.
[42]  林 宙輝, 橋本 昌宜, 小野寺 秀俊, ``セルベース設計環境を用いた高性能データパス設計法の検討,'' 情報処理学会DAシンポジウム, pp. 113-118, July 2002.
[43]  山口 隼司, 橋本 昌宜, 小野寺 秀俊, ``IRドロップを考慮した電源線構造の最適化手法,'' 情報処理学会DAシンポジウム, pp. 253-258, July 2002.
[44]  平松 大輔, 土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``長距離高速信号伝送を可能にするVLSI配線構造の検討,'' 情報処理学会DAシンポジウム, pp. 155-160, July 2002.
[45]  山田 祐嗣, 橋本 昌宜, 小野寺 秀俊, ``ゲート出力波形導出時の誤差要因とその影響の評価,'' 2002年電子情報通信学会総合大会講演論文集, no. A-3-3, p. 82, March 2002.
[46]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``LSI配線インダクタンスに対する直交配線の影響,'' 2002年電子情報通信学会総合大会講演論文集, no. A-3-23, p. 102, March 2002.
[47]  藤森 一憲, 橋本 昌宜, 小野寺 秀俊, ``駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発,'' 電子情報通信学会VLSI設計技術研究会, no. VLD2001-147/ICD2001-222, March 2002.
[48]  橋本 昌宜, 高橋 正郎, 小野寺 秀俊, ``ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法,'' 情報処理学会システムLSI設計技術研究会(デザインガイア), no. SLDM103-6, pp. 39-44, November 2001.
[49]  土谷 亮, 橋本 昌宜, 小野寺 秀俊, ``長距離高速配線における RC モデルに基づく回路設計の限界,'' 2001年電子情報通信学会ソサイエティ大会講演論文集, no. A-3-6, p. 60, September 2001.
[50]  高橋 正郎, 橋本 昌宜, 小野寺 秀俊, ``波形重ね合せによるクロストーク遅延変動量の見積もり手法,'' 2001年電子情報通信学会ソサイエティ大会講演論文集, no. A-3-9, p. 63, September 2001.
[51]  橋本 昌宜, 高橋 正郎, 小野寺 秀俊, ``ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法,'' 2001年電子情報通信学会ソサイエティ大会講演論文集, no. A-3-8, p. 62, September 2001.
[52]  高橋 正郎, 橋本 昌宜, 小野寺 秀俊, ``隣接位置を考慮した解析的クロストークノイズ見積もり手法,'' 情報処理学会DAシンポジウム, pp. 19-24, July 2001.
[53]  橋本 昌宜, 高橋 正郎, 小野寺 秀俊, ``隣接位置を考慮した解析的クロストークノイズモデル ---実回路への 適用---,'' 2001年電子情報通信学会総合大会講演論文集, no. A-3-6, p. 84, March 2001.
[54]  高橋 正郎, 橋本 昌宜, 小野寺 秀俊, ``隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 ---,'' 2001年電子情報通信学会総合大会講演論文集, no. A-3-5, p. 83, March 2001.
[55]  橋本 昌宜, 小野寺 秀俊, ``パスバランス回路における遅延不確かさの統計的解析,'' 電子情報通信学会VLSI設計技術研究会(デザインガイア), no. VLD2000-72, November 2000.
[56]  橋本 昌宜, 小野寺 秀俊, ``パスバランス回路における遅延不確かさの統計的解析,'' 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, no. A-3-9, p. 76, September 2000.
[57]  橋本 昌宜, 小野寺 秀俊, ``セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法,'' 情報処理学会DAシンポジウム, pp. 185-190, July 2000.
[58]  橋本 昌宜, 小野寺 秀俊, ``静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法,'' 第13回 回路とシステム(軽井沢)ワークショップ, pp. 137-142, April 2000.
[59]  橋本 昌宜, 小野寺 秀俊, ``静的統計遅延解析を用いた最悪遅延時間計算手法,'' 2000年電子情報通信学会総合大会講演論文集, no. A-3-13, p. 81, March 2000.
[60]  橋本 昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺 秀俊, ``オンデマンドライブラリを用いたシステムLSI詳細設計手法,'' 電子情報通信学会VLSI設計技術研究会, no. VLD99-112/ICD99-269, March 2000.
[61]  橋本 昌宜, 橋本 鉄太郎，西川 亮太，福田 大輔，黒田 慎介， 菅 俊介，神原 弘之，小野寺 秀俊, ``オンデマンドライブラリを用いたシステムLSI詳細設計手法,'' 第3回 システムLSI琵琶湖ワークショップ, pp. 279-281, November 1999.
[62]  橋本 昌宜, 小野寺 秀俊, ``スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討,'' 1999年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, no. A-3-9, p. 52, September 1999.
[63]  橋本 昌宜, 小野寺 秀俊, 田丸 啓吉, ``グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用---,'' 1998年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, no. A-3-5, September 1998.
[64]  橋本 昌宜, 小野寺 秀俊, 田丸 啓吉, ``グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法,'' 情報処理学会DAシンポジウム, pp. 269-274, July 1998.
[65]  橋本 昌宜, 小野寺 秀俊, 田丸 啓吉, ``論理シミュレーションを用いた消費電力見積もりの高精度化手法,'' 1998年電子情報通信学会総合大会講演論文集, no. A-3-5, p. 91, March 1998.
[66]  橋本 昌宜, 小野寺 秀俊, 田丸 啓吉, ``入力端子接続最適化による遅延時間と消費電力の最適化手法,'' 1997年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, no. A-3-15, p. 67, September 1997.
[67]  橋本 昌宜, 小野寺 秀俊, 田丸 啓吉, ``入力端子接続最適化による消費電力削減手法,'' 情報処理学会DAシンポジウム, pp. 99-104, July 1997.

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