- 論文誌
- [1]
D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, (to appear).
- [2]
T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,'' IEICE Trans. on Information and Systems , (to appear).
- [3]
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices,'' IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
- 国際会議
- [1]
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices,'' Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012.
- [2]
T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.
- [3]
D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability,'' IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.
- [4]
D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Soft Error Resilient Vlsi Architecture for Signal Processing,'' Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 183--186, December 2009.
- [5]
D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.
- [6]
Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 236--241, March 2009.
- [7]
D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability,'' Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
- 国内会議(査読付き)
- [1]
郡浦宏明, D. Alnajjar, 高永勲, 今川隆司, 廣本正之, 密山幸男, 橋本昌宜, 越智裕之, 尾上孝雄, ``柔軟な信頼性を実現する粗粒度再構成可能アーキテクチャ,'' LSIとシステムのワークショップ, pp. 191--193, May 2010.
- [2]
高 永勲, Dawood Alnajjar, 密山幸男, 橋本昌宜, 尾上孝雄, ``柔軟な信頼性を実現する粗粒度再構成可能アーキテクチャの検討,'' 電子情報通信学会ディペンダブルコンピューティング研究会, no. DC2008-41, November 2008.
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