- 論文誌
- [1]
T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, ``Impact of Self-Heating in Wire Interconnection on Timing,'' IEICE Trans. on Electronics, vol. E93-C, no. 3, pp. 388--392, March 2010.
- [2]
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, ``Modeling the Overshooting Effect for Cmos Inverter Delay Analysis in Nanometer Technologies,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 29, no. 2, pp. 250--260, February 2010.
- [3]
T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, ``An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3016--3023, December 2009.
- [4]
A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto, ``Interconnect Modeling: a Physical Design Perspective (Invited),'' IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1840--1851, September 2009.
- [5]
T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, ``Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. 92-A, no. 4, pp. 990--997, April 2009.
- [6]
T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M Hashimoto, ``Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3666-3670, December 2006.
- [7]
A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, , Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, ``Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3453-3462, December 2005.
- [8]
金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜, ``遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法,'' 情報処理学会論文誌, vol. 44, no. 5, pp. 1301-1310, May 2003.
- 国際会議
- [1]
K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 47-53, November 2006.
- [2]
K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations,'' In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 59-64, February 2006.
- [3]
T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, and M. Hashimoto, ``Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149-155, January 2003.
- 国内会議(査読付き)
- [1]
新開 健一, 橋本 昌宜, 黒川 敦, 尾上 孝雄, ``電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル,'' 第19回 回路とシステム(軽井沢)ワークショップ, pp. 559-564, April 2006.
- [2]
金本 俊幾, 阿久津滋聖, 中林 太美世, 一宮 敬弘, 蜂屋 孝太郎, 石川 博, 室本 栄, 小林 宏行, 橋本 昌宜, 黒川 敦, ``遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価,'' 情報処理学会DAシンポジウム, pp. 265-270, July 2004.
- [3]
佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, ``インダクタンスに起因する配線遅延変動の統計的予測手法,'' 2002年電子情報通信学会ソサイエティ大会講演論文集, no. TA-2-4, pp. 247-248, September 2002.
- [4]
金本 俊幾, 佐藤 高史, 黒川 敦, 川上 善之, 岡 宏規, 北浦 智靖, 池内 敦彦, 小林 宏行, 橋本 昌宜, ``0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法,'' 情報処理学会DAシンポジウム, pp. 149-154, July 2002.
- [5]
佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, ``インダクタンスが配線遅延に及ぼす影響の定量的評価方法,'' 第15回 回路とシステム(軽井沢)ワークショップ, pp. 493-498, April 2002.
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