Selected Publications of Takao ONOYE 


Journal Publications

  1. T. Onoye, A. Yamada, I. Arungsrisangchai, M. Tanaka and I. Shirakawa: "An automatic layout generator for bipolar analog modules," IEICE Trans. Fundamentals, vol. E75-A, no. 10, pp. 1306-1314, Oct. 1992.
  2. T. Onoye, T. Masaki, I. Shirakawa, H. Hirata, K. Kimura, S. Asahara, and T. Sagishima: "High-level synthesis of a multithreaded processor for image generation," IEICE Trans. Fundamentals, vol. E78-A, no. 3, pp. 322-330, March 1995.
  3. T. Masaki, Y. Morimoto, T. Onoye, and I. Shirakawa: "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding," IEEE Trans. Circuits and Systems for Video Technology, vol. 5, no. 5, pp. 387-395, Oct. 1995.
  4. T. Onoye, T. Masaki, Y. Morimoto, Y. Sato, I. Shirakawa, and K. Matsumura: "Single chip implementation of MPEG2 decoder for HDTV level pictures," IEICE Trans. Fundamentals, vol. E79-A, no. 3, pp. 330-338, March 1996.
  5. T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai: "Single chip implementation of motion estimator dedicated to MPEG2 MP@HL," IEICE Trans. Fundamentals, vol. E79-A, no. 8, pp. 1210-1216, Aug. 1996.
  6. T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami: "Voice and telephony over ATM for multimedia network using shared VCI cell," Journal of Circuits, Systems and Computers, vol. 7, no. 2, pp. 93-110, April 1997.
  7. 吉田幸弘，宋宝玉，奥畑宏之，尾上孝雄，白川功: "組込み用プロセッサの低消費電力化に関する一手法," 電子情報通信学会論文誌}, vol. J80-A, no. 5, pp. 765-771, May 1997 (in Japanese). 
  8. K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa: "Single chip implementation of encoder-decoder for low bitrate visual communication," Journal of Circuits, Systems and Computers, vol. 7, no. 5, pp. 441-457, Oct. 1997.
  9. T. Masaki, Y. Nakatani, T. Onoye, N. Yamai, and K. Murakami: "Voice communication on multimedia ATM network using shared VCI cell," IEICE Trans. Communications, vol. E81-B, no. 2, pp. 340-346, Feb. 1998.
  10. 木村浩三，奥畑宏之，尾上孝雄，白川功，清原督三，鷺島敬之: "マルチスレッドプロセッサのデータキャッシュ制御方式," 映像情報メディア学会誌, vol. 52, no. 5, pp. 742-749, May 1998 (in Japanese).
  11. G. Fujita, T. Onoye, and I. Shirakawa: "A VLSI architecture for motion estimation core dedicated to H.263 video coding," IEICE Trans. Electronics, vol. E81-C, no. 5, pp. 702-707, May 1998.
  12. H. Okuhata, M.H. Miki, T. Onoye, and I. Shirakawa: "A low-power DSP architecture for low bitrate speech codec," IEICE Trans. Fundamentals, vol. E81-A, no. 8, pp. 1616-1621, Aug. 1998.
  13. M.H. Miki, 藤田玄，尾上孝雄，白川功: "携帯端末向け低電力H.263 コーデック・コアのVLSI化設計," 電子情報通信学会論文誌, vol. J81-A, no. 10, pp. 1352-1361, Oct. 1998 (in Japanese).
  14. H. Fujishima, Y. Takemoto, T. Onoye, and I. Shirakawa: "An architecture of matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics," IEEE Trans. Circuits and Systems for Video Technology, vol. 9, no. 2, pp. 306-314, March 1999.
  15. B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa: "Low-power scheme of NMOS 4-phase dynamic logic," IEICE Trans. Electronics, vol. E82-C, no. 9, pp. 1772-1776, Sept. 1999.
  16. J. Fan, G. Fujita, M. Furuie, T. Onoye, I. Shirakawa, and L. Wu: "Automatic moving object extraction toward compact video representation," Optical Engineering, vol. 39, no. 2, pp. 438-452, Feb. 2000.
  17. M. Hatanaka, T. Masaki, T. Onoye, and K. Murakami: "VLSI architecture of switching control for AAL type2 switch," IEICE Trans. Fundamentals, vol. E83-A, no. 3, pp. 435-441, March 2000.
  18. B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa: "Low-power VLSI implementation by NMOS 4-phase dynamic logic," Trans. IPSJ, vol. 41, no. 4, pp. 899-907, April 2000.
  19. J. Fan, J. Yu, G. Fujita, T. Onoye, L. Wu, and I. Shirakawa: "Spatiotemporal segmentation for compact video representation," Signal Processing: Image Communication, vol. 16, no. 6, pp. 553-566, Feb. 2001.
  20. Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa: "A novel dynamically reconfigurable hardware-based cipher," Trans. IPSJ, vol. 42, no. 4, pp. 958-966, April 2001.
  21. W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa: "3D acoustic image localization algorithm by embedded DSP," IEICE Trans. Fundamentals, vol. E84-A, no. 6, pp. 1423-1430, June 2001.
  22. H. Tsutsui, A. Tomita, S. Sugimoto, K. Sakai, T. Izumi, T. Onoye, and Y. Nakamura: "LUT-array-based PLD and synthesis approach based on sum of generalized complex terms expression," IEICE Trans. Fundamentals, vol. E84-A, no. 11, pp. 2681-2689, Nov. 2001.
  23. R.Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa: "An embedded zerotree wavelet video coding algorithm with reduced memory bandwidth requirements," IEICE Trans. Fundamentals, vol. E85-A, no. 3, pp. 703-713, March 2002.
  24. 宋天, 藤田玄, 尾上孝雄, 白川功: "携帯端末用低消費電力 H.263 Version 2 コーデックコアのVLSI化設計," 情報処理学会論文誌, vol. 43, no. 4, pp. 1161-1170, May 2002 (in Japanese).
  25. H. Okada, A.E. Shiitev, H.S. Song, G. Fujita, T. Onoye, and I. Shirakawa: "Error detection by digital watermarking for MPEG-4 video coding," IEICE Trans. Fundamentals, vol. E85-A, no. 6, pp. 1281-1288, June 2002.
  26. 岡田浩行, 宋学燮, 藤田玄, 尾上孝雄, 白川功: "電子透かしのMPEG-4ビットストリームエラー検出への応用," 画像電子学会誌,, vol. 31, no. 5, pp. 900-908, Sept. 2002 (in Japanese). 
  27. Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, I. Shirakawa: "Wireless digital video transmission system using IEEE802.11b PHY with error correctio block based ARQ protocol," IEICE Trans. Communications, vol. E85-B, no. 10, pp. 2032-2043, Oct. 2002.
  28. H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa: "Performance estimation at architecture level for embedded systems," IEICE Trans. Fundamentals, vol. E85-A, no. 12, pp. 2636-2644, Dec. 2002.
  29. N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "Single DSP implementation of realtime 3D sound synthesis algorithm," Journal of Circuits, Systems and Computers, vol. 12, no. 1, pp. 55-73, Feb. 2003.
  30. K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa: "Object sharing scheme for heterogenous environment," IEICE Trans. Fundamentals, vol. E86-A, no. 4, pp. 813-821, April 2003.
  31. T. Okamoto, T. Yuasa, T. Izumi, T. Onoye, and Y. Nakamura: "Design tools and trial design for PCA-Chip2," IEICE Trans. Information and Systems, vol. E86-D, no. 5, pp. 868-871, May 2003.
  32. N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa: " Embedded implementation of acoustic field enhancement for stereo sound sources," IEEE Trans. Consumer Electronics, vol. 49, no. 3, pp. 737-741, Aug. 2003.
  33. 宋学燮, 岡田浩行, 藤田玄, 尾上孝雄, 白川功: "MPEG-4動画像符号化向けハイブリッドエラー隠蔽方式," 画像電子学会誌, vol. 32, no. 5, pp. 609-620, Sept. 2003. 
  34. 小谷章夫, 小山至幸, 密山幸男, 尾上孝雄: "低解像度表示デバイス向けフォントLCFONTの重心および可読性の評価," 画像電子学会誌, vol. 32, no. 5, pp. 621-628, Sept. 2003.
  35. M. Kimura, M.H. Miki, T. Onoye, and I. Shirakawa: "Implementation of Java accelerator for high performance embedded systems," IEICE Trans. Fundamentals, vol. E86-A, no. 12, pp. 3079-3088, Dec. 2003.
  36. 岡田勉, 内田翼, 尾上孝雄, 白川功: "次世代GNSS受信機用信号処理機構とそのVLSI化設計," 電子情報通信学会論文誌, vol. J86-A, no. 12, pp. 1417-1425, Dec. 2003.
  37. T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa: "Embedded 3D sound movement system based on feature extraction of head-related transfer function," IEEE Transactions on Consumer Electronics, vol. 51, no. 1, pp. 262-267, Feb. 2005.
  38. Y. Mituyama, M. Kimura, T. Onoye, I. Shirakawa: "Architecture of IEEE802.11i cipher algorithms for embedded systems," IEICE Trans. Fundamentals, vol. E88-A, no. 4, pp. 899-906, April 2005.
  39. K. Tsujino, K. Furuya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura: "Design of realtime 3-D sound processing system," IEICE Trans. Information and Systems, vol. E88-D, no. 5, pp.954-962, May 2005.
  40. A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa: "Desing of Ogg Vorbis decoder system for embedded platform," IEICE Trans. Fundamentals, vol. E88-A, no. 8, pp. 2124-2130, Aug. 2005.
  41. 藤田玄, 尾上孝雄, 白川功: "MPEG-4向け高精度動き検出コアのVLSI化設計," 電子情報通信学会論文誌, vol. J88-A, no. 11, pp. 1282-1291, Nov. 2005.
  42. Z. Guo, Y. Nishikawa, R.Y. Omaki, T. Onoye, and I. Shirakawa: "A low-complexity FEC assignment scheme for Motion JPEG2000 over wireless network," IEEE Trans. Consumer Electronics, vol. 52, no. 1, pp. 81-86, Feb. 2006.
  43. M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa: "W-CDMA channel codec by configurable processors," Journal of Intelligent Automation and Soft Computing, vol.13, no. 3, pp. 318-330, March 2006.
  44. H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura: "Design framework for JPEG2000 system architecture," Journal of Intelligent Automation and Soft Computing, vol. 13, no. 3, pp. 331-343, March 2006.
  45. G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa: "Real-time human object extraction method for mobile systems based on color space segmentation," IEICE Trans. Fundamentals, vol. E89-A, no. 4, pp. 941-949, April 2006.
  46. 小谷章夫, 種村嘉高, 密山幸男, 朝井宣実, 中村安久, 尾上孝雄: "ポテンシャルエネルギーを用いた文字重心位置取得手法," 画像電子学会誌, vol. 35, no. 4, pp.296-305, Sept. 2006.
  47. K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi: "An energy-efficient architecture of wireless home network based on MAC broadcast and transmission power control," IEEE Trans. Consumer Electronics, vol. 53, no. 1, pp. 124-130, Feb. 2007.
  48. K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura: "Efficient 3-D sound movement with time-varying IIR filters," IEICE Trans. Fundamentals, vol. E90-A, no. 3, pp. 618-624, March 2007.
  49. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Quantitative prediction of on-chip capacitive and inductive crosstalk noise and tradeoff between wire cross sectional area and inductive crosstalk effect," IEICE Trans. Fundamentals, vol. E90-A, no. 4, pp. 724-731, April 2007.
  50. K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura: "Automatic filter design for 3-D sound movement in embedded applications," Acoustical Science and Technology, vol. 28, no. 4, pp. 219-229, July 2007.
  51. M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa: "Design and implementation of home network protocol for appliance control based on IEEE 802.15.4," International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.
  52. Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye: "Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement," IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, no. 10, pp. 868-872,October 2007.
  53. N. Iwanaga, T. Matsumura, A. Yoshida, W. Kobayashi, and T. Onoye: "Embedded system implementation of sound localization in proximal region," IEICE Trans. Fundamentals vol. E91-A, no. 3, pp. 763-771,March 2008.
  54. Y. Ogasahara, M. Hashimoto, and T. Onoye: "Measurement and analysis of inductive coupling noise in 90nm global interconnects," IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718-728,March 2008.
  55. R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye: "Implementation of multi-agent object attention system based on biologically inspired attractor selection," IEICE Trans. Fundamentals, vol. E91-A, no. 10, October 2008. 
  56. Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa: "Area-efficient reconfigurable architecture for media processing," IEICE Trans. Fundamentals, vol. E91-A, no. 12, pp. 3651-3662, December 2008.
  57. S. Abe, M. Hashimoto, and T. Onoye: "Clock skew evaluation considering manufacturing variability in mesh-style clock distribution," IEICE Trans. Fundamentals, vol. E91-A, no. 12, pp. 3481-3487, December 2008.
  58. T. Masuzaki, H. Tsutsui, Q.M. Vu, T. Onoye, and Y. Nakamura: "JPEG2000 high-speed SNR progressive decoding scheme," International Journal of Computer Science and Network Security, vol. 9, no. 1, pp. 62-68, January 2009. 
  59. K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "An experimental study on body-biasing layout style focusing on area efficiency and speed controllability," IEICE Trans. Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.
  60. 増崎隆彦, 筒井弘, 尾上孝雄, 水野雄介, 佐々木元, 中村行宏: "シングルタイ ル JPEG2000 コーデックのシステム構成," 画像電子学会誌, vol. 38, no. 3, pp. 296-304, May 2009. 
  61. Y. Ogasahara, M. Hashimoto, T. Onoye: "All digital ring-oscillator based macro for sensing dynamic supply noise waveform," IEEE Journal of Solid-State Circuits, vol. 44, no. 6, pp. 1745-1755, June 2009.
  62. H. Sugano, T. Masuzaki, H. Tsutsui, T. Onoye, H. Ochi, and Y. Nakamura, "Efficient memory organization framework for JPEG2000 entropy codec," IEICE Trans. Fundamentals, vol. E92-A, no. 8, pp. 1970-1977, August 2009. 
  63. 畠中理英, 達可敏充, 渡邊賢治, 尾上孝雄: "透過減衰を考慮した無線ホーム ネットワーク向け位置推定," 情報処理学会論文誌, vol. 50, no. 8, pp. 1835-1844, August 2009.
  64. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction," IEICE Trans. Fundamentals, vol. E92-A, no. 12, pp. 3094-3102, December 2009. 
  65. K. Shinkai, M. Hashimoto, and T. Onoye: "Prediction of self-heating in short intra-block wires," IEICE Trans. Fundamentals, vol. E93-A, no. 3, pp. 583-594, March 2010.
  66. 渡邊賢治, 達可敏充, 畠中理英, 尾上孝雄: "屋内位置推定システムのための間 取り推定手法," Journal of Signal Processing, vol. 14, no. 3, pp. 231-242, May 2010. 
  67. 密山幸男, 高橋一真, 今井林太郎, 橋本昌宜, 尾上孝雄, 白川功: "メディア処 理向け再構成可能アーキテクチャでの動画像復号処理の実現," 電子情報通信学 会論文誌, vol. J93-A, no. 6, pp. 397-413, June 2010. 
  68. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye: "Transistor variability modeling and its validation with ring-oscillation frequencies for body-biased subthreshold circuits," IEEE Transactions on VLSI Systems, vol. 18, no. 7, pp. 1118-1129, July 2010.
  69. 大原一人, 芥子育雄, 尾上孝雄: "映像コンテンツ同時閲覧のための負荷適応デ コーダ制御手法," 画像電子学会誌, vol. 39, no. 6, pp. 1095-1103, November 2010.
  70. M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi: "3D sound rendering for multiple sound sources based on Fuzzy clustering," IEICE Trans. Fundamentals, vol. E93-A, no. 11, pp. 2163-2172, November 2010.
  71. R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye: "Measurement circuits for acquiring SET pulse width distribution with sub-FO1-inverter-delay resolution," IEICE Trans. Fundamentals, vol. E93-A, no. 12, pp. 2417-2423, December 2010.


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