著者名 (author) 表題 (title) 論文誌/会議名 巻数 (volume) 号数 (number) ページ範囲 (pages) 刊行月 (month) 出版年 (year) File
論文誌
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
Supply Noise Suppression by Triple-Well Structure
IEEE Transactions on VLSI Systems
21
4
781--785
April
2013

論文誌
Y. Ogasahara, M. Hashimoto, T. Onoye
All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform
IEEE Journal of Solid-State Circuits
44
6
1745--1755
June
2009

論文誌
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
Impact of Well Edge Proximity Effect on Timing
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
3461-3464
December
2008

論文誌
Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects
IEEE Journal of Solid-State Circuits
43
3
718-728
March
2008

論文誌
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement
IEEE Trans. on Circuits and Systems—II: Express Briefs
54
10
868-872
October
2007

論文誌
M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, I. Shirakawa
Design and Implementation of Home Network Protocol for Appliance Control Based on {IEEE} 802.15.4
International Journal of Computer Science and Network Security
7
7
20-30
July
2007

論文誌
Y. Ogasahara, M. Hashimoto, T. Onoye
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E90-A
4
724--731
April
2007

論文誌
M. Ise, Y. Ogasahara, T. Onoye, I. Shirakawa
W-{CDMA} Channel codec by configurable processors
Intelligent Automation and Soft Computing
12
3
317--29

2006

国際会議
Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement of On-chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase due to SSO
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)


19--20
May
2010

国際会議
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)


397--400
November
2008

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification
Proc. IEEE/ACM Asia and South Pacific Design Automation Conference


107-108
January
2008

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect
Proc. IEEE Custom Integrated Circuits Conference


783-786
September
2007

国際会議
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
Impact of Well Edge Proximity Effect on Timing
Proc. IEEE European Solid-State Device Research Conference


115-118
September
2007

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects
Proc. IEEE International Conference on Computer Design


70--75
October
2006

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects
Proc. IEEE Custom Integrated Circuits Conference


721--724
September
2006

国際会議
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-Chip Simulation
Proc.~IEEE Custom Integrated Circuits Conference


861--864
September
2006

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement and Analysis of Delay Variation due to Inductive Coupling
Proc. IEEE Custom Integrated Circuits Conference


305--308
September
2005

国際会議
Y. Ogasahara, M. Ise, T. Onoye, I. Shirakawa
Architecture of Turbo Decoder for W-{CDMA} by Configurable Processor
Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4


7
July
2004

国際会議
M. Ise, Y. Ogasahara, T. Onoye, I. Shirakawa
Implementation of W-{CDMA} Channel Codec by Configurable Processors
Proc. Sixth Baiona Workshop on Signal Processing in Communications


205--210
September
2003

研究会等発表論文
小笠原泰弘, 橋本昌宜, 尾上孝雄
バス配線による誘導性クロストークノイズによる遅延変動の実測とノイズ重ねあわせ効果の検証




March
2008

研究会等発表論文
小笠原 泰弘, 橋本 昌宜, 尾上 孝雄
スタンダードセルで構成された電源ノイズ波形測定回路の提案
信学技報, CPM2007-131, ICD2007-142


17-22
January
2008

研究会等発表論文
小笠原 泰弘, 橋本 昌宜, 尾上 孝雄
90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測
信学技報, CPM2006-131, ICD2006-173


13--18
January
2007

研究会等発表論文
小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄
電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法
信学技報, CPM2006-132, ICD2006-174


19--23
January
2007

研究会等発表論文
小笠原泰弘, 橋本昌宜, 尾上孝雄
{LSI}配線における容量性, 誘導性クロストークノイズの定量的将来予測
第19回回路とシステム軽井沢ワークショップ


5--10
April
2006

研究会等発表論文
伊勢正尚, 小笠原泰弘, 渡邊賢治, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功
{IEEE} 802.15.4を用いたホームネットワーク向け無線ネットワークプロトコル
信学技報, CAS2005-99


19--24
March
2006

研究会等発表論文
小笠原泰弘, 橋本昌宜, 尾上孝雄
誘導性・容量性クロストークノイズによる遅延変動の測定と評価
信学技報, SDM2005-135, ICD2005-74


43--48
August
2005

研究会等発表論文
盧 承烈, 小笠原 泰弘, 伊勢 正尚, 畠中 理英, 尾上 孝雄, 庭本 浩明, 芥子 育雄, 白川 功
ユニバーサルプラグアンドプレイ技術を用いたホームネットワーク一構成方式
信学技報, CAS2004-68


7--12
January
2005


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