著者名 (author) 表題 (title) 論文誌/会議名 巻数 (volume) 号数 (number) ページ範囲 (pages) 刊行月 (month) 出版年 (year) File
論文誌
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
Supply Noise Suppression by Triple-Well Structure
IEEE Transactions on VLSI Systems
21
4
781--785
April
2013

論文誌
T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto
Impact of Self-heating in Wire Interconnection on Timing
IEICE Trans. on Electronics
E93-C
3
388--392
March
2010

論文誌
T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E92-A
12
3016--3023
December
2009

論文誌
A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto
Interconnect Modeling: A Physical Design Perspective (Invited)
IEEE Transactions on Electron Devices
56
9
1840--1851
September
2009

論文誌
T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
92-A
4
990--997
April
2009

論文誌
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
Impact of Well Edge Proximity Effect on Timing
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
3461-3464
December
2008

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560--3568
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in SoC Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, M Hashimoto
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3666-3670
December
2006

国際会議
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)


397--400
November
2008

国際会議
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
Impact of Well Edge Proximity Effect on Timing
Proc. IEEE European Solid-State Device Research Conference


115-118
September
2007

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)


227--230
May
2006

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction
The 3rd International Workshop on Compact Modeling


51--56
January
2006


This site is maintained by Onoye Lab.

PMAN 2.5.5 - Paper MANagement system / (C) 2002-2008, Osamu Mizuno / All rights reserved.