著者名 (author) 表題 (title) 論文誌/会議名 巻数 (volume) 号数 (number) ページ範囲 (pages) 刊行月 (month) 出版年 (year) File
論文誌
S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye
Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator
IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences
E98-A
12
2607--2613
December
2015

論文誌
D. Fukuda, K. Watanabe, Y. Kanazawa, M. Hashimoto
Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification
IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences
E98-A
7
1467--1474
July
2015

論文誌
T. Shinada, M. Hashimoto, T. Onoye
Proximity Distance Estimation based on Electric Field Communication between 1mm³ Sensor Nodes
Analog Integrated Circuits and Signal Processing



May
2015

論文誌
S. Hirokawa, R. Harada, M. Hashimoto, T. Onoye
Characterizing alpha- and neutron-induced SEU and MCU on SOTB and bulk 0.4-V SRAMs
IEEE Transactions on Nuclear Science



April
2015

論文誌
H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
12
2518--2529
December
2014

論文誌
T. Amaki, M. Hashimoto, T. Onoye
A Process and Temperature Tolerant Oscillator-based True Random Number Generator
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
12
2393--2399
December
2014

論文誌
D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, M. Hashimoto
Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
12
2373--2382
December
2014

論文誌
T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, M. Hashimoto
Exploring Well-Configurations for Minimizing Single Event Latchup
IEEE Transactions on Nuclear Science
61
6
3282--3289
December
2014

論文誌
H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, T. Onoye
Comparative evaluation of lifetime enhancement with fault avoidance on dynamically reconfigurable devices
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
7
1468--1482
July
2014

論文誌
H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, T. Onoye
NBTI mitigation method by inputting random scan-in vectors in standby time
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
7
1483--1491
July
2014

論文誌
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-die Process Variation Effects
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
7
1461--1467
July
2014

論文誌
H. Fuketa, R. Harada, M. Hashimoto, T. Onoye
Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM
IEEE Transactions on Device and Materials Reliability
14
1
463 -- 470
March
2014

論文誌
D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, T. Onoye
Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture
IEEE Transactions on VLSI Systems
21
12
2165 -- 2178
December
2013

論文誌
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch
IEEE Transactions on Nuclear Science
60
6
4362--4367
December
2013

論文誌
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment
IEEE Transactions on Nuclear Science
60
6
4232--4237
December
2013

論文誌
K. Shinkai, M. Hashimoto, T. Onoye
A Gate-Delay Model Focusing on Current Fluctuation over Wide Range of Process-Voltage-Temperature Variations
Integration, the VLSI Journal
46
4
345--358
September
2013

論文誌
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Impact of {NBTI}-Induced Pulse-Width Modulation on {SET} Pulse-Width Measurement
IEEE Transactions on Nuclear Science
60
4
2630--2634
August
2013

論文誌
T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices
IEICE Trans. on Information and Systems
E96-D
8
1624--1631
August
2013

論文誌
T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye
A Worst-case-aware Design Methodology for Noise-tolerant Oscillator-based True Random Number Generator with Stochastic Behavior Modeling
IEEE Transactions on Information Forensics and Security
8
8
1331--1342
August
2013

論文誌
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
Supply Noise Suppression by Triple-Well Structure
IEEE Transactions on VLSI Systems
21
4
781--785
April
2013

論文誌
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
PVT-induced Timing Error Detection through Replica Circuits and Time Redundancy in Reconfigurable Devices
IEICE Electronics Express (ELEX)
10
5

April
2013

論文誌
I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, T. Onoye
A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation
IEICE Electronics Express (ELEX)
10
4

March
2013

論文誌
T. Amaki, M. Hashimoto, T. Onoye
Jitter Amplifier for Oscillator-based True Random Number Generator
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E96-A
3
684--696
March
2013

論文誌
I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye
Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E96-A
2
459--468
February
2013

論文誌
T. Enami, T. Sato, M. Hashimoto
Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E95-A
12
2261--2271
December
2012

論文誌
Y. Takai, M. Hashimoto, T. Onoye
Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E95-A
12
2220--2225
December
2012

論文誌
S. Kimura, M. Hashimoto, T. Onoye
A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E95-A
12
2292--2300
December
2012

論文誌
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
IEEE Transactions on Nuclear Science
59
6
2791--2795
December
2012

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
IEEE Transactions on VLSI Systems
20
2
333--343
February
2012

論文誌
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
Stress Probability Computation for Estimating {NBTI}-Induced Delay Degradation
IEICE Trans. Fundamentals
E94-A
12
2545-2553
December
2011

論文誌
K. Shinkai, M. Hashimoto, T. Onoye
Extracting Device-Parameter Variations with RO-Based Sensors
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E94-A
12
2537--2544
December
2011

論文誌
T. Okumura, M. Hashimoto
Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E94-A
10
1948--1953
October
2011

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
IEEE Transactions on Nuclear Science
58
4
2097--2102
August
2011

論文誌
H. Fuketa, D. Kuroda, M. Hashimoto, T. Onoye
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion
IEEE Transactions on Circuits and Systems II
58
5
299--303
May
2011

論文誌
T. Enami, S. Ninomiya, K. Shinkai, S. Abe, M. Hashimoto
Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences
93-A
12
2399-2408
December
2010

論文誌
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Measurement Circuits for Acquiring {SET} Pulse Width Distribution with Sub-{FO1}-inverter-delay Resolution
IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences
E93-A
12
2417-2423
December
2010
論文誌
S. Ninomiya, M. Hashimoto
Accuracy Enhancement of Grid-based SSTA by Coefficient Interpolation
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E93-A
12
2441--2446
December
2010

論文誌
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto
Gate Delay Estimation in STA under Dynamic Power Supply Noise
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E93-A
12
2447--2455
December
2010

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Transistor Variability Modeling and Its Validation with Ring-oscillation Frequencies for Body-biased Subthreshold Circuits
IEEE Transactions on VLSI Systems
18
7
1118--1129
July
2010

論文誌
密山 幸男, 高橋 一真, 今井 林太郎, 橋本 昌宜, 尾上 孝雄, 白川 功
メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現
電子情報通信学会論文誌
J93-A
6
397-413
June
2010

論文誌
K. Shinkai, M. Hashimoto, T. Onoye
Prediction of Self-Heating in Short Intra-Block Wires
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences
E93-A
3
583-594
March
2010
論文誌
T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto
Impact of Self-heating in Wire Interconnection on Timing
IEICE Trans. on Electronics
E93-C
3
388--392
March
2010

論文誌
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
29
2
250--260
February
2010

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences
E92-A
12
3094-3102
December
2009

論文誌
T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E92-A
12
3016--3023
December
2009

論文誌
A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto
Interconnect Modeling: A Physical Design Perspective (Invited)
IEEE Transactions on Electron Devices
56
9
1840--1851
September
2009

論文誌
Y. Ogasahara, M. Hashimoto, T. Onoye
All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform
IEEE Journal of Solid-State Circuits
44
6
1745--1755
June
2009

論文誌
T. Enami, S. Ninomiya, M. Hashimoto
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
28
4
541-553
April
2009

論文誌
T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
92-A
4
990--997
April
2009

論文誌
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
IEICE Trans. on Electronics
E92-C
2
281-285
February
2009

論文誌
密山 幸男, 高橋 一真, 今井 林太郎, 橋本 昌宜, 尾上 孝雄, 白川 功
Area-Efficient Reconfigurable Architecture for Media Processin
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
3651-3662
December
2008

論文誌
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
Impact of Well Edge Proximity Effect on Timing
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
3461-3464
December
2008

論文誌
S. Abe, M. Hashimoto, T. Onoye
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
3481-3487
December
2008

論文誌
M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
3474-3480
December
2008

論文誌
R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, T. Onoye
Implementation of Multi-Agent Object Attention System based on Biologically Inspired Attractor Selection
IEICE Trans. Fundamentals
E91-A
10

October
2008

論文誌
Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects
IEEE Journal of Solid-State Circuits
43
3
718-728
March
2008

論文誌
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
Timing Analysis Considering Temporal Supply Voltage Fluctuation
IEICE Trans. on Information and Systems
E91-D
3
655--660
March
2008

論文誌
M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, I. Shirakawa
Transistor Sizing of {LCD} Driver Circuit for Technology Migration
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E90-A
12
2712--2717
December
2007

論文誌
M. Hashimoto, J. Yamaguchi, H. Onodera
Timing Analysis Considering Spatial Power/Ground Level Variation
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E90-A
12
2661-2668
December
2007

論文誌
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement
IEEE Trans. on Circuits and Systems—II: Express Briefs
54
10
868-872
October
2007

論文誌
A. Tsuchiya, M. Hashimoto, H. Onodera
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling
IEICE Trans. on Electronics
E90-C
6
1267-1273
June
2007

論文誌
Y. Ogasahara, M. Hashimoto, T. Onoye
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E90-A
4
724--731
April
2007

論文誌
S. Takahashi, S. Tsukiyama, M. Hashimoto, I. Shirakawa
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3538--3545
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560--3568
December
2006

論文誌
S. Takahashi, S. Tsukiyama, M. Hashimoto, I. Shirakawa
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3538-3545
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in SoC Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
T. Sato, J. Ichimiya, N. Ono, M. Hashimoto
On-chip thermal gradient analysis considering interdependence between leakage power and temperature
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3491-3499
December
2006

論文誌
T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, M Hashimoto
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3666-3670
December
2006

論文誌
内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功
グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積りの容易化
情報処理学会論文誌
47
6
1665--1673
June
2006

論文誌
M. Hashimoto, T. Yamamoto, H. Onodera
Statistical Analysis of Clock Skew Variation in H-tree Structure
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3375-3381
December
2005

論文誌
A. Muramatsu, M. Hashimoto, H. Onodera
Effects of On-chip Inductance on Power Distribution Grid
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3564-3572
December
2005

論文誌
T. Sato, M. Hashimoto, H. Onodera
Successive pad assignment for minimizing supply voltage drop
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3429-3436
December
2005

論文誌
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto
On-chip thermal gradient analysis and temperature flattening for SoC design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3382-3389
December
2005

論文誌
A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, , Y. Yang, Y. Inoue, R. Inagaki, H. Masuda
Second-order Polynomial Expressions for On-chip Interconnect Capacitance
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3453-3462
December
2005

論文誌
内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功
システム液晶のための配線容量抽出手法
情報処理学会論文誌
46
6
1395--1403
June
2005

論文誌
A. Tsuchiya, M. Hashimoto, H. Onodera
Performance Limitation of On-chip Global Interconnects for High-Speed Signaling
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science
E88-A
4
885-891
April
2005

論文誌
T. Miyazaki, M. Hashimoto, H. Onodera
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and An LC Oscillator Based PLL
IEICE Trans. on Electronics
E88-C
3
437-444
March
2005

論文誌
M. Hashimoto, H. Onodera
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E87-A
12
3251-3257
December
2004

論文誌
M. Hashimoto, Y. Yamada, H. Onodera
Equivalent Waveform Propagation for Static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
23
4
498-508
April
2004

国際会議
R. Shirai, T. Hirose, M. Hashimoto
{Dedicated Antenna Less Power Efficient OOK Transmitter for mm-Cubic IoT Nodes}
Proceedings of the 47th European Microwave Conference (EuMC)


101--104
October
2017

国際会議
M. Hashimoto, R. Shirai, Y. Itoh, T. Hirose
Toward Real-time 3D Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited)
Proceedings of IEEE International Conference on ASIC


1087--1091
October
2017

国際会議
R. Shirai, J. Kono, T. Hirose, M. Hashimoto
Near-Field Dual-Use Antenna for Magnetic-Field Based Communication and Electrical-Field Based Distance Sensing in mm^3-Class Sensor Node
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)


124--127
May
2017

国際会議
Y. Masuda, M. Hashimoto, T. Onoye
Measurement of Timing Error Detection Performance of Software-based Error Detection Mechanisms and Its Correlation with Simulation
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)


28-35
March
2016

国際会議
R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto
Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)



March
2016

国際会議
U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, B. Li
Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited)
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


705--711
January
2016

国際会議
N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi Author(s) in English
A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs
Technical Digest of IEEE International Electron Devices Meeting (IEDM)


32--35
December
2015

国際会議
Y. Masuda, M. Hashimoto, T. Onoye
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise
Proceedings of International Conference on Computer-Aided Design (ICCAD)


315-322
November
2015

国際会議
R. Doi, M. Hashimoto, T. Onoye
An Analytic Evaluation on Soft Error Immunity Enhancement due to Temporal Triplication
IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)



November
2015

国際会議
S. Iizuka, Y. Masuda, M. Hashimoto, T. Onoye
Stochastic Timing Error Rate Estimation under Process and Temporal Variations
Proceedings of International Test Conference (ITC)



October
2015

国際会議
Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, M. Hashimoto
A Wireless Power Transfer System for Small-Sized Sensor Applications
Proceedings of International Conference on Solid State Devices and Materials (SSDM)


154--155
September
2015

国際会議
S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, Y. Watanabe
Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation
IEEE Nuclear and Space Radiation Effects Conference (NSREC)



July
2015

国際会議
M. Ueno, M. Hashimoto, T. Onoye
Real-time On-chip Supply Voltage Sensor and Its Application to Trace-based Timing Error Localization
Proceedings of International On-Line Testing Symposium (IOLTS)


188--193
July
2015

国際会議
M. Hashimoto
Run-time Performance Adaptation: Opportunities and Challenges (Invited)
Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC)



June
2015

国際会議
T. Uemura, T. Kato, S. Okano, H. Matsuyama, M. Hashimoto
Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM
Proceedings of International Symposium on Reliability Physics (IRPS)



April
2015

国際会議
T. Uemura, M. Hashimoto
Investigation of Single Event Upset and Total Ionizing Dose in FeRAM for Medical Electronic Tag
Proceedings of International Symposium on Reliability Physics (IRPS)



April
2015

国際会議
T. Uemura, S. Okano, T. Kato, H. Matsuyama, M. Hashimoto
Soft Error Immune Latch Design for 20 nm bulk CMOS
Proceedings of International Reliability Physics Symposium (IRPS)



April
2015

国際会議
S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, T. Onoye
3D Node Localization from Node-to-Node Distance Information using Cross-Entropy Method
Proceedings of Virtual Reality Conference (VR)



March
2015

国際会議
S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye
Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


731--736
January
2015

国際会議
M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, H. Onodera
Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


14--15
January
2015

国際会議
T. Amaki, M. Hashimoto, T. Onoye
An Oscillator-based True Random Number Generator with Process and Temperature Tolerance
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


4--5
January
2015

国際会議
M. Hashimoto
Stochastic Verification of Run-time Performance Adaptation with Field Delay Testing (Invited)
Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS)


751--754
November
2014

国際会議
M. Hashimoto
Opportunities and Verification Challenges of Run-time Performance Adaptation (Invited)
Proceedings of Asian Test Symposium (ATS)


248--253
November
2014

国際会議
M. Hashimoto
Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective (Invited)
Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)



October
2014

国際会議
A. Iokibe, M. Hashimoto, T. Onoye
Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground
Proceedings of International Conference on Sensing Technology (ICST)


188--193
September
2014

国際会議
T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, M. Hashimoto
Optimizing Well-Configuration for Minimizing Single Event Latchup
IEEE Nuclear and Space Radiation Effects Conference (NSREC)



July
2014

国際会議
R. Harada, S. Hirokawa, M. Hashimoto
Measurement of Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4 V SRAMs
IEEE Nuclear and Space Radiation Effects Conference (NSREC)



July
2014

国際会議
T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, K. Hatanaka
Preventing Single Event Latchup with Deep P-well on P-substrate
Proceedings of International Reliability Physics Symposium (IRPS)



June
2014

国際会議
M. Ueno, M. Hashimoto, T. Onoye
Trace-based fault localization with supply voltage sensor
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)



March
2014

国際会議
Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design
ReConFig



December
2013

国際会議
D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)


313-316
November
2013

国際会議
T. Amaki, M. Hashimoto, T. Onoye
A process and temperature tolerant oscillator-based true random number generator with dynamic 0/1 bias correction
Proceedings of Asian Solid-State Circuits Conference (A-SSCC)


133-136
November
2013

国際会議
S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, T. Onoye
Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing
Proc. International Conference on Computer-Aided Design (ICCAD)


107-114
November
2013

国際会議
J. Kono, M. Hashimoto, T. Onoye
Feasibility Evaluation of Near-Field Communication in Clay with 1-mm^3 Antenna
Proceedings of Asia-Pacific Microwave Conference (APMC)


1121--1123
November
2013

国際会議
R. Harada, M. Hashimoto, T. Onoye
NBTI Characterization Using Pulse-Width Modulation
IEEE/ACM Workshop on Variability Modeling and Characterization



November
2013

国際会議
M. Hashimoto
Soft Error Immunity of Subthreshold SRAM (Invited)
Proceedings of IEEE International Conference on ASIC


91--94
October
2013

国際会議
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor reliability on Bulk CMOS Technology
IEEE Nuclear and Space Radiation Effects Conference (NSREC)



July
2013

国際会議
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
Soft-Error in SRAM at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment
IEEE Nuclear and Space Radiation Effects Conference (NSREC)



July
2013

国際会議
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch
IEEE Nuclear and Space Radiation Effects Conference (NSREC)



July
2013

国際会議
T. Shinada, M. Hashimoto, T. Onoye
Proximity Distance Estimation Based on Capacitive Coupling Between 1mm^3 Sensor Nodes
Proceedings of International NEWCAS Conference



June
2013

国際会議
M. Ueno, M. Hashimoto, T. Onoye
Real-time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures
Proceedings of Reconfigurable Architectures Workshop (RAW)


301--305
May
2013

国際会議
Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, S. Nassif
Extracting Device-Parameter Variations using a Single Sensitivity-Configurable Ring Oscillator
Proceedings of IEEE European Test Symposium (ETS)


106--111
May
2013

国際会議
M. Hashimoto
Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (Invited)
China Semiconductor Technology International Conference (CSTIC)


1079--1084
March
2013

国際会議
河野 仁, 橋本 昌宜, 尾上 孝雄
Feasibility Evaluation of Near-Field Communication in Clay with 1-mm3 Antenna
Microwave Conference Proceedings (APMC), 2013 Asia-Pacific


1121-1123

2013

国際会議
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
Static Voltage Over-scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices
Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)



December
2012

国際会議
I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye
Signal-Dependent Analog-to-Digital Converter Based on MINIMAX Sampling
Proceedings of International SoC Design Conference (ISOCC)


120 -- 123
November
2012

国際会議
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Impact of NBTI-­Induced Pulse-Width Modulation on SET Pulse-Width Measurement
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)



September
2012

国際会議
T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture
Proceedings of International Conference on Field Programmable Logic and Applications (FPL)



August
2012

国際会議
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
IEEE Nuclear and Space Radiation Effects Conference



July
2012

国際会議
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
SET Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-die Process Variation Effects
Proceedings of International Reliability Physics Symposium (IRPS)



April
2012

国際会議
K. Watanabe, G. Fujita, T. Homemoto, R. Hashimoto
A High-speed H.264/{AVC} {CABAC} Decoder for {4K} Video Utilizing Residual Data Accelerator
The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012)


6-10
March
2012

国際会議
S. Kimura, M. Hashimoto, T. Onoye
Body Bias Clustering for Low Test-Cost Post-Silicon Tuning
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


283--289
February
2012

国際会議
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
Implications of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures
Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece


189-194
September
2011

国際会議
Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode
PATMOS2011



September
2011

国際会議
Y. Takai, M. Hashimoto, T. Onoye
Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)



September
2011

国際会議
M. Hashimoto, H. Fuketa
Adaptive Performance Compensation with On-Chip Variation Monitoring (invited)
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)



August
2011

国際会議
I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye
Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)



August
2011

国際会議
T. Amaki, M. Hashimoto, T. Onoye
An Oscillator-Based True Random Number Generator with Jitter Amplifier
Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2011)


725-728
May
2011

国際会議
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Neutron Induced Single Event Multiple Transients With Voltage Scaling and Body Biasing
Proc. International Reliability Physics Symposium (IRPS)



April
2011

国際会議
S. Kimura, M. Hashimoto, T. Onoye
Body Bias Clustering for Low Test-Cost Post-Silicon Tuning
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)


46--51
April
2011

国際会議
K. Shinkai, M. Hashimoto, T. Onoye
Extracting Device-Parameter Variations with RO-Based Sensors
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)


13--18
March
2011

国際会議
D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
MTTF Measurement Under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability
IEEE Workshop on Silicon Errors in Logic - System Effects



March
2011

国際会議
T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye
A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling
Proc. International Workshop on Information Security Applications (WISA 2010)


107-121
January
2011

国際会議
T. Amaki, M. Hashimoto, T. Onoye
Jitter Amplifier for Oscillator-Based True Random Number Generator
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2011)


81-82
January
2011

国際会議
K. Shinkai, M. Hashimoto
Device-Parameter Estimation with On-chip Variation Sensors Considering Random Variability
Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)


683-688
January
2011
国際会議
M. Hashimoto
Run-Time Adaptive Performance Compensation using On-chip Sensors (Invited)
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


285--290
January
2011

国際会議
M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, S. Sampei
{VLSI} Design of {OFDM} Baseband Transceiver with Dynamic Spectrum Access
Proc. of the 18th International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2010)


329-332
December
2010

国際会議
Y. Takai, M. Hashimoto, T. Onoye
Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation
Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)


213--216
October
2010

国際会議
T. Okumura, M. Hashimoto
Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)



September
2010

国際会議
K. Shinkai, M. Hashimoto
Self-Heating in Nano-Scale VLSI Interconnects
Proceedings of International Workshop on Information Communication Technology (ICT)


S-1-6
August
2010
国際会議
S. Abe, K. Shinkai, M. Hashimoto, T. Onoye
Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-chip Sensors
Proc. Great Lakes Symposium on VLSI (GLSVLSI)



May
2010

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
Proceedings of International Reliability Physics Symposium (IRPS)


213--217
May
2010

国際会議
Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement of On-chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase due to SSO
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)


19--20
May
2010

国際会議
D. Kuroda, H. Fuketa, M. Hashimoto, T. Onoye
A 16-bit RISC Processor with 4.18pJ/cycle at 0.5V Operation
Proceedings of IEEE COOL Chips


190
April
2010

国際会議
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration
Proc. International Symposium on Quality Electronic Design (ISQED)


646-651
March
2010

国際会議
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Measurement Circuits for Acquiring {SET} Pulse Width Distribution with Sub-{FO1}-inverter-delay Resolution
Proc. International Symposium on Quality Electronic Design (ISQED)



March
2010
国際会議
T. Enami, S. Ninomiya, K. Shinkai, S. Abe, M. Hashimoto
Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)


41-46
March
2010

国際会議
S. Abe, K. Shinkai, M. Hashimoto, T. Onoye
Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors
Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)



March
2010

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)


361-362
January
2010

国際会議
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto
Gate Delay Estimation in STA under Dynamic Power Supply Noise
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


775 -- 780
January
2010

国際会議
D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
Soft Error Resilient VLSI Architecture for Signal Processing
Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)


183--186
December
2009

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits
Proc. IEEE Custom Integrated Circuits Conference


215-218
September
2009

国際会議
R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, S. Sampei
Implementation of OFDM Baseband Transceiver with Dynamic Spectrum Access for Cognitive Radio Systems
Proc. of 9th International Symposium on Communication and Information Technology (ISCIT2009)


658-663
September
2009

国際会議
S. Ninomiya, M. Hashimoto
Enhancement of Grid-based Spatially-Correlated Variability Modeling for Improving SSTA Accuracy
Proceedings of IEEE International SOC Conference (SOCC)


337--340
September
2009

国際会議
K. Hamamoto, M. Hashimoto, Y. Mitsuyama, T. Onoye
Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)


51--56
August
2009

国際会議
D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
Coarse-grained Dynamically Reconfigurable Architecture with Flexible Reliability
Proceedings of International Conference on Field Programmable Logic and Applications (FPL)


186--192
August
2009

国際会議
S. Watanabe, M. Hashimoto, T. Sato
A Case for Exploiting Complex Arithmetic Circuits towards Performance Yield Enhancement
Proceedings of International Symposium on Quality Electronic Design (ISQED)


401--407
March
2009

国際会議
Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)


236--241
March
2009

国際会議
D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability
Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE)



March
2009

国際会議
K. Shinkai, M. Hashimoto
A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability
Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)


79-84
February
2009
国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Trade-off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)


266-271
January
2009

国際会議
L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, C-K Cheng
High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


385--390
January
2009

国際会議
T. Enami, M. Hashimoto, T. Sato
Decoupling Capacitance Allocation {for} Timing {with} Statistical Noise Model {and} Timing Analysis
Proc. IEEE/ACM International Conference on Computer-Aided Design


420-425
November
2008

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-biased Circuits and Subthreshold Circuits
ICCAD Colocated Workshop on Test Structure Design for Variability Characterization



November
2008

国際会議
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)


397--400
November
2008

国際会議
Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, C.-K. Cheng
On-Chip High Performance Signaling using Passive Compensation
Proceedings of IEEE International Conference on Computer Design (ICCD)


182-187
October
2008

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits
Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)


3-8
August
2008

国際会議
S. Watanabe, M. Hashimoto, T. Sato
Cascading Dependent Operations for Mitigating Timing Variability
Proceedings. of Workshop on Quality-Aware Design (W-QUAD)



June
2008

国際会議
S. Takahashi, S. Tsukiyama, M. Hashimoto, I. Shirakawa
A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays
In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)



June
2008

国際会議
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -
ACM Great Lakes Symposium on VLSI


387-390
May
2008

国際会議
T. Enami, S. Ninomiya, M. Hashimoto
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
Proc. ACM International Symposium on Physical Design


160-167
April
2008
国際会議
S. Abe, M. Hashimoto, T. Onoye
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
Proc. International Symposium on Quality Electronic Design (ISQED)


520-525
March
2008

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification
Proc. IEEE/ACM Asia and South Pacific Design Automation Conference


107-108
January
2008

国際会議
L. Zhang, J. Liu, H. Zhu, C-K Cheng, M. Hashimoto
High Performance Current-Mode Differential Logic
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


720--725
January
2008

国際会議
R. Hashimoto, K. Kato, G. Fujta, T. Onoye
{VLSI} ARCHITECTURE OF H.264 {RDO}-BASED BLOCK SIZE DECISION FOR 1080 {HD}
Proc. PCS



November
2007

国際会議
R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, T. Onoye
Implementation of Object Attention based on Multi-Agent Attractor Selection
Proc. SISB



November
2007

国際会議
K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, T.Onoye
A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007)


233-237
October
2007

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect
Proc. IEEE Custom Integrated Circuits Conference


783-786
September
2007

国際会議
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
Impact of Well Edge Proximity Effect on Timing
Proc. IEEE European Solid-State Device Research Conference


115-118
September
2007

国際会議
M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration
Proc. IEEE Custom Integrated Circuits Conference


869-872
September
2007

国際会議
K. Shinkai, M. Hashimoto, T. Onoye
Future Prediction of Self-heating in Short Intra-block Wires
Proc. International Symposium on Quality Electronic Design (ISQED)


660-665
March
2007

国際会議
R. Hashimoto, K. Kato, G. Fujta, T. Onoye
{VLSI} Architecture of H.264 Block Size Decision based on Rate-Distortion Optimization
Proc. ISPACS


618--621
December
2006

国際会議
K. Shinkai, M. Hashimoto, A. Kurokawa, T. Onoye
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process and Environmental Variability
Proc. International Conference on Computer-Aided Design (ICCAD)


47-53
November
2006

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects
Proc. IEEE International Conference on Computer Design


70--75
October
2006

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects
Proc. IEEE Custom Integrated Circuits Conference


721--724
September
2006

国際会議
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-Chip Simulation
Proc.~IEEE Custom Integrated Circuits Conference


861--864
September
2006

国際会議
T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, I. Shirakawa
Transistor Sizing of Lcd Driver Circuit for Technology Migration
Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
1

I25--I28
July
2006

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)


227--230
May
2006

国際会議
K. Shinkai, M. Hashimoto, A. Kurokawa, T. Onoye
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process and Environmental Variability
Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)


59-64
February
2006

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction
The 3rd International Workshop on Compact Modeling


51--56
January
2006

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Interconnect RL Extraction at a Single Representative Frequency
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


515-520
January
2006

国際会議
S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa
A Sampling Switch Design for Liquid Crystal Displays
Proceedings of IEEE International Region 10 Conference



November
2005

国際会議
T. Kouno, M. Hashimoto, H. Onodera
Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)


453-456
November
2005

国際会議
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
Performance Prediction of On-chip High-throughput Global Signaling
Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)


79-82
October
2005

国際会議
Y. Ogasahara, M. Hashimoto, T. Onoye
Measurement and Analysis of Delay Variation due to Inductive Coupling
Proc. IEEE Custom Integrated Circuits Conference


305--308
September
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)


613-616
September
2005

国際会議
S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa
A Design Scheme for Sampling Switch in Active Matrix LCD
A Design Scheme for Sampling Switch in Active Matrix LCD



August
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Substrate Loss of On-chip Transmission-lines with Power/Ground Wires in Lower Layer
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)


Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)
May
2005

国際会議
Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa
Interconnect capacitance extraction for system {LCD} circuits
in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005)


160--163
April
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics
Proceedings of International Meeting for Future of Electron Devices, Kansai


33-34
April
2005

国際会議
A. Muramatsu, M. Hashimoto, H. Onodera
Effects of On-chip Inductance on Power Distribution Grid
Proceedings of International Symposium on Physical Design (ISPD)


63-69
April
2005

国際会議
M. Hashimoto, T. Yamamoto, H. Onodera
Statistical Analysis of Clock Skew Variation in H-tree Structure
Proceedings of International Symposium on Quality Electronic Design (ISQED)


402-407
March
2005

国際会議
T. Sato, M. Hashimoto, H. Onodera
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


723-728
January
2005

国際会議
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
Timing Analysis Considering Temporal Supply Voltage Fluctuation
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


1098-1101
January
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Return Path Selection for Loop RL Extraction
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


1078-1081
January
2005

国際会議
T. Sato, N. Ono, J. Ichimiya, K. Hachiya, M. Hashimoto
On-chip thermal gradient analysis and temperature flattening for SoC design
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


1074-1077
January
2005

国際会議
A. Shinmyo, M. Hashimoto, H. Onodera
Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


D9-D10
January
2005

国際会議
S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa
A Sampling Switch Design for Liquid Crystal Displays
Proceedings of IEEE International Region 10 Conference, 1C-03.3




2005

国際会議
S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa
A Design Scheme for Sampling Switch in Active Matrix {LCD}
Proceedings of European Conference on Circuit Theory and Design, 3e-212




2005

国際会議
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
Performance Prediction of On-chip Global Signaling
IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)


87-100
November
2004

国際会議
M. Hashimoto, J. Yamaguchi, H. Onodera
Timing Analysis Considering Spatial Power/Ground Level Variation
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)


814-820
November
2004

国際会議
M. Hashimoto, A. Tsuchiya, H. Onodera
On-Chip Global Signaling by Wave Pipelining
IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)


311-314
October
2004

国際会議
A. Muramatsu, M. Hashimoto, H. Onodera
LSI Power Network Analysis with On-chip Wire Inductance
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)


55-60
October
2004

国際会議
T. Sato, M. Hashimoto, H. Onodera
An IR-drop minimization by optimizing number and location of power supply pads
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)


66-72
October
2004

国際会議
M. Hashimoto, T. Yamamoto, H. Onodera
Statistical Analysis of Clock Skew Variation
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)


214-219
October
2004

国際会議
T. Miyazaki, M. Hashimoto, H. Onodera
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and An LC Oscillator Based PLL
IEEJ International Analog VLSI Workshop


45-50
October
2004

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Performance Limitation of On-chip Global Interconnects for High-speed Signaling
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)


489-492
September
2004

国際会議
A. Shinmyo, M. Hashimoto, H. Onodera
Design and Optimization of CMOS Current Mode Logic Dividers
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits


434-435
August
2004

国際会議
S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, I. Shirakawa
{VLSI} Implementation of Portable {MPEG}-4 Audio Decoder
in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA


80--84
September
2000

国内会議(査読付き)
小島康介, 橋本亮司, 藤田玄
H.264 向け量子化パラメータを考慮した動きベクトル検出手法の一検討
第22回 回路とシステム軽井沢ワークショップ


142-147
April
2009

研究会等発表論文
白井 僚,廣瀬 哲也,橋本 昌宜
超小型IoTノード向けアンテナ組み込み型OOKトランスミッタの実装と評価
第45回アナログRF研究会


2
March
2017

研究会等発表論文
S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye
Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator
電子情報通信学会 VLSI設計技術研究会



March
2015

研究会等発表論文
郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄
動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討
信学技報, RECONF2013-8
113
52
41-46
May
2013

研究会等発表論文
天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄
確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法
信学技報, VLD2012-154
112
451
099-104
March
2013

研究会等発表論文
郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄
動的部分再構成による故障回避に関する一考察
信学技報, RECONF2012-59
112
325
71-76
November
2012

研究会等発表論文
天木 健彦, 橋本 昌宜, 尾上 孝雄
ゆらぎ増幅回路を用いたオシレータベース物理乱数生成器
信学技報, ICD2011-118
111
352
087-092
December
2011

研究会等発表論文
亀田 敏広, 郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄
スキャンパスを用いたNBTI劣化抑制に関する研究
情報処理学会DAシンポジウム


201-206
August
2011

研究会等発表論文
郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄
動的再構成可能アーキテクチャによる故障回避機構の定量的評価
信学技報, RECONF2011-6
111
31
31-36
May
2011

研究会等発表論文
天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄
確率的動作モデルを用いたオシレータベース物理乱数生成器の設計手法
情報処理学会研究報告, SLDM2010-147
2010-SLDM-147
19
1-6
November
2010

研究会等発表論文
榎並 孝司, 木村 修太, 橋本 昌宜, 尾上 孝雄
自己性能補償に向けたカナリアFF挿入手法
情報処理学会DAシンポジウム


227-232
September
2010

研究会等発表論文
高井 康充, 橋本 昌宜, 尾上 孝雄
電源ノイズに注目した電源遮断法の実機評価


信学技報 vol.110, No344


2010

研究会等発表論文
黒田 弾, 更田 裕司, 橋本 昌宜, 尾上 孝雄
低エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価
情報処理学会第141回システムLSI設計技術研究会, pp107-112



October
2009

研究会等発表論文
新開 健一, 橋本 昌宜
広範囲な製造・環境ばらつきに対応したゲート遅延モデル
情報処理学会DAシンポジウム


73-78
August
2009

研究会等発表論文
郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄
NBTI による劣化予測におけるトランジスタ動作確率算出法の評価
情報処理学会DAシンポジウム


181-186
August
2009

研究会等発表論文
橋本 昌宜, 榎並 孝司, 新開 健一, 二宮 進有, 阿部 慎也
電源ノイズや製造ばらつきによるクロックジッタ・スキューを考慮した統計的タイミング解析
情報処理学会DAシンポジウム


79-84
August
2009

研究会等発表論文
天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄
マルコフモデルによるオシレータサンプリング方式真性乱数生成器の乱数品質解析
第22回回路とシステム軽井沢ワークショップ


474-479
April
2009

研究会等発表論文
達可敏充, 橋本亮司, 渡邊賢治, 畠中理英, 尾上孝雄
ダイナミックスペクトルアクセスを用いたコグニティブ無線ネットワークにおけるノード位置推定手法の一検討
信学技報, IN2008-220
108
458
523-528
March
2009

研究会等発表論文
濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄
レイアウトを考慮した基板バイアスクラスタリング手法
信学技報, VLD2008-159
108
478
195-200
March
2009

研究会等発表論文
榎並 孝司, 橋本 昌宜, 佐藤 高史
電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法
信学技報, VLD2008-161
108
478
207-212
March
2009

研究会等発表論文
更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証
信学技報, VLD2008-159
108
478
201-206
March
2009

研究会等発表論文
橋本亮司, 筒井 弘, 尾上孝雄, 猪飼知宏
{DCT}領域 Distributed Video Coding における尤度推定手法
信学技報, IE2008-209
108
425
31-36
February
2009

研究会等発表論文
小島康介, 橋本亮司, 藤田玄
H.264向けRDOに基づいた動きベクトル検出手法の一検討
電子情報通信学会技術研究報告, SIP2008-99
104
213
53-58
September
2008

研究会等発表論文
更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析
情報処理学会DAシンポジウム


217-222
August
2008

研究会等発表論文
濱本 浩一, 更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
基板バイアス印加レイアウト方式の面積効率と速度制御性の評価
信学技報, CAS2008-14, VLD2008-27, SIP2008-48(2008-6)


75-79
June
2008

研究会等発表論文
小笠原泰弘, 橋本昌宜, 尾上孝雄
バス配線による誘導性クロストークノイズによる遅延変動の実測とノイズ重ねあわせ効果の検証




March
2008

研究会等発表論文
小笠原 泰弘, 橋本 昌宜, 尾上 孝雄
スタンダードセルで構成された電源ノイズ波形測定回路の提案
信学技報, CPM2007-131, ICD2007-142


17-22
January
2008

研究会等発表論文
二宮 進有, 橋本 昌宜
{SSTA}における空間的相関を持つ製造ばらつきのグリッドベースモデル化法の検討
信学技報, VLD2007-91, DC2007-46
107
336
13-17
November
2007

研究会等発表論文
橋本亮司, 加藤公也, 才辻誠, 田中照人, 上津寛和, 藤田玄, 尾上孝雄
1080HD向けマルチシンボルH.264エントロピー復号器
第21回ディジタル信号処理シンポジウム



November
2007

研究会等発表論文
加藤 公也, 橋本 亮司, 藤田 玄, 尾上 孝雄
H.264 High ProfileにおけるマルチシンボルCABAC復号器のアーキテクチャ検討
信学技報, SIP2007-121, ICD2007-110, IE2007-80


65-70
October
2007

研究会等発表論文
橋本 昌宜
製造・環境ばらつきを考慮したタイミング検証技術
信学技報, VLD2007-65


21-24
October
2007

研究会等発表論文
阿部 慎也, 橋本 昌宜, 尾上 孝雄
製造ばらつきを考慮したメッシュ型クロック分配網のスキュー評価
情報処理学会DAシンポジウム


133-138
August
2007

研究会等発表論文
新開 健一, 橋本 昌宜, 尾上 孝雄
短距離ブロック内配線の自己発熱
第 20 回 回路とシステム軽井沢ワークショップ


7-12
April
2007

研究会等発表論文
榎並 孝司, 二宮 進有, 橋本 昌宜
電源ノイズの空間的相関を考慮した統計的タイミング解析
第20回 回路とシステム軽井沢ワークショップ


667-672
April
2007

研究会等発表論文
橋本 昌宜
製造・環境ばらつきと動的性能補償を考慮したタイミング検証に向けて
第20回 回路とシステム(軽井沢)ワークショップ


661-666
April
2007

研究会等発表論文
小笠原 泰弘, 橋本 昌宜, 尾上 孝雄
90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測
信学技報, CPM2006-131, ICD2006-173


13--18
January
2007

研究会等発表論文
小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄
電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法
信学技報, CPM2006-132, ICD2006-174


19--23
January
2007

研究会等発表論文
橋本 亮司, 藤田 玄, 尾上 孝雄
H.264符号化における演算量動的割当ての一手法
第21回ディジタル信号処理シンポジウム, D8-1



November
2006

研究会等発表論文
Jangsombatsiri Siriporn, 橋本 昌宜, 尾上 孝雄
シャントコンダクタンスを挿入したオンチップ伝送線路特性評価
第十回シリコンアナログRF研究会



November
2006

研究会等発表論文
榎並 孝司, 橋本 昌宜, 尾上 孝雄
主成分分析による電源電圧変動の統計的モデル化手法
情報処理学会DAシンポジウム


205--210
July
2006

研究会等発表論文
新開 健一, 橋本 昌宜, 黒川 敦, 尾上孝雄
電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル
第19回 回路とシステム軽井沢ワークショップ


559-564
April
2006

研究会等発表論文
小笠原泰弘, 橋本昌宜, 尾上孝雄
{LSI}配線における容量性, 誘導性クロストークノイズの定量的将来予測
第19回回路とシステム軽井沢ワークショップ


5--10
April
2006

研究会等発表論文
伊地知孝仁, 橋本昌宜, 高橋真吾, 築山修治, 白川功
画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術
信学技報, VLD2005-131


55--60
March
2006

研究会等発表論文
小笠原泰弘, 橋本昌宜, 尾上孝雄
誘導性・容量性クロストークノイズによる遅延変動の測定と評価
信学技報, SDM2005-135, ICD2005-74


43--48
August
2005

研究会等発表論文
内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功
システム液晶のための配線間容量抽出手法
信学技報, VLD2004-64


19--24
December
2004

研究会等発表論文
丹羽 章雅, 橋本 晋弥, 奥畑 宏之, 尾上 孝雄, 白川 功
携帯用 {MPEG}-4 オーディオデコーダの {VLSI} 化設計
第14回ディジタル信号処理シンポジウム


629--634
November
1999

著書
M. Hashimoto, R. Nair
Power Integrity for Nanoscale Integrated Systems
McGraw-Hill Professional



February
2014

大会等発表論文
橋本 亮司, 達可 敏充, 畠中 理英, 尾上 孝雄, 畑本 浩伸, 衣斐 信介, 宮本 伸一, 三瓶 政一
ダイナミックスペクトルアクセスを用いたOFDM無線送受信機のFPGA実装
電子情報通信学会総合大会, AS-2-2



March
2010

大会等発表論文
中村 秀幸, 筒井 弘, 橋本 亮司, 尾上 孝雄
特徴点追跡を用いた動き補償フレーム補間手法
電子情報通信学会2009ソサイエティ大会, A-20-14


204
September
2009

大会等発表論文
橋本 亮司, 加藤 公也, 藤田 玄, 尾上 孝雄
H.264 CABAC復号器の高速化に関する一検討
電子情報通信学会2008ソサイエティ大会,A-20-9



September
2008

大会等発表論文
橋本亮司, 藤田玄, 尾上孝雄
1080HD向けH.264 CAVLC復号器の高速化に関する一検討
電子情報通信学会2007ソサイエティ大会,A-20-16



September
2007

大会等発表論文
榎並 孝司, 橋本 昌宜
統計的電源ノイズモデル化に適した適応的領域分割法
電子情報通信学会ソサイエティ大会


A-3-10
September
2007

大会等発表論文
河村 侑輝, 橋本 亮司, 尾上孝雄
H.264符号化における1/4画素精度動き検出の性能評価
電子情報通信学会2007ソサイエティ大会,A-4-28



September
2007

大会等発表論文
橋本亮司, 松村友哉, 野里良裕, 渡邊賢治, 尾上孝雄
複眼光学系による物体注視システムのハードウェア実現
第9回 DSPS教育者会議 予稿集


87-88
August
2007

大会等発表論文
二宮 進有, 橋本 昌宜
空間的相関を考慮した{SSTA}における領域の分割数と精度
電子情報通信学会総合大会, A-3-1



March
2007

大会等発表論文
濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄
低電圧回路向け基板電位制御レイアウト方式の面積効率評価
電子情報通信学会総合大会, A-3-6



March
2007

大会等発表論文
阿部 慎也, 橋本 昌宜, 尾上 孝雄
メッシュ型クロック分配網のスキュー評価
電子情報通信学会総合大会, A-3-5



March
2007

大会等発表論文
更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
加算器を用いたsubthreshold 回路の設計指針の検討
電子情報通信学会総合大会, A-3-17



March
2007

大会等発表論文
Siriporn Jangsombatsiri, 橋本昌宜, 土谷亮, Haikun Zhu, Chung-Kuan Cheng
シャントコンダクタンスを挿入したオンチップ伝送線路のアイパターン評価
電子情報通信学会総合大会, A-3-9



March
2007

大会等発表論文
新開 健一, 橋本 昌宜, 尾上 孝雄
短距離ブロック内配線の自己発熱問題の将来予測
電子情報通信学会ソサイエティ大会


A-3-14
September
2006

大会等発表論文
加藤 公也, 橋本 亮司, 藤田 玄, 尾上 孝雄
時間的・空間的隣接ヘッダ情報に基づくH.264イントラ予測モード判定手法
電子情報通信学会ソサイエティ大会



September
2006

大会等発表論文
榎並 孝司, 橋本 昌宜, 尾上 孝雄
電源ノイズ解析のための回路動作部表現法の評価
電子情報通信学会総合大会, A-3-16



March
2006

大会等発表論文
橋本 亮司, 藤田 玄, 尾上 孝雄
動画像の動き量に基づくH.264符号化パラメータ設定手法
電子情報通信学会総合大会, D-11-42



March
2006

大会等発表論文
高橋 真吾, 築山 修治, 橋本 昌宜, 白川 功
液晶ディスプレイ用サンプリング回路の設計手法について
2005 年電子情報通信学会ソサイエティ大会講演論文集, A-3-4




2005

大会等発表論文
内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功
システム液晶に適した配線間容量抽出の検討
電子情報通信学会ソサイエティ大会, A-1-16



September
2004

大会等発表論文
橋本 晋弥, 丹羽 章雅, 奥畑 宏之, 尾上 孝雄, 白川 功
{MPEG}-4 オーディオデコーダにおけるノイズレス復号器およびスペクトル 予測器の {VLSI} 化設計
信学会 ソサイエティ大会, A-3-4



September
1999


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