著者名 (author) 表題 (title) 論文誌/会議名 巻数 (volume) 号数 (number) ページ範囲 (pages) 刊行月 (month) 出版年 (year) File
論文誌
H. Fuketa, R. Harada, M. Hashimoto, T. Onoye
Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM
IEEE Transactions on Device and Materials Reliability
14
1
463 -- 470
March
2014

論文誌
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
IEEE Transactions on Nuclear Science
59
6
2791--2795
December
2012

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
IEEE Transactions on VLSI Systems
20
2
333--343
February
2012

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
IEEE Transactions on Nuclear Science
58
4
2097--2102
August
2011

論文誌
H. Fuketa, D. Kuroda, M. Hashimoto, T. Onoye
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion
IEEE Transactions on Circuits and Systems II
58
5
299--303
May
2011

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Transistor Variability Modeling and Its Validation with Ring-oscillation Frequencies for Body-biased Subthreshold Circuits
IEEE Transactions on VLSI Systems
18
7
1118--1129
July
2010

論文誌
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences
E92-A
12
3094-3102
December
2009

論文誌
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
IEICE Trans. on Electronics
E92-C
2
281-285
February
2009

国際会議
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
IEEE Nuclear and Space Radiation Effects Conference



July
2012

国際会議
M. Hashimoto, H. Fuketa
Adaptive Performance Compensation with On-Chip Variation Monitoring (invited)
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)



August
2011

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
Proceedings of International Reliability Physics Symposium (IRPS)


213--217
May
2010

国際会議
D. Kuroda, H. Fuketa, M. Hashimoto, T. Onoye
A 16-bit RISC Processor with 4.18pJ/cycle at 0.5V Operation
Proceedings of IEEE COOL Chips


190
April
2010

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)


361-362
January
2010

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits
Proc. IEEE Custom Integrated Circuits Conference


215-218
September
2009

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Trade-off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)


266-271
January
2009

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-biased Circuits and Subthreshold Circuits
ICCAD Colocated Workshop on Test Structure Design for Variability Characterization



November
2008

国際会議
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits
Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)


3-8
August
2008

国際会議
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -
ACM Great Lakes Symposium on VLSI


387-390
May
2008

国際会議
K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, T.Onoye
A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007)


233-237
October
2007

研究会等発表論文
黒田 弾, 更田 裕司, 橋本 昌宜, 尾上 孝雄
低エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価
情報処理学会第141回システムLSI設計技術研究会, pp107-112



October
2009

研究会等発表論文
更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証
信学技報, VLD2008-159
108
478
201-206
March
2009

研究会等発表論文
更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析
情報処理学会DAシンポジウム


217-222
August
2008

研究会等発表論文
濱本 浩一, 更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
基板バイアス印加レイアウト方式の面積効率と速度制御性の評価
信学技報, CAS2008-14, VLD2008-27, SIP2008-48(2008-6)


75-79
June
2008

大会等発表論文
更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄
加算器を用いたsubthreshold 回路の設計指針の検討
電子情報通信学会総合大会, A-3-17



March
2007


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