著者名 (author) 表題 (title) 論文誌/会議名 巻数 (volume) 号数 (number) ページ範囲 (pages) 刊行月 (month) 出版年 (year) File
論文誌
M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
3474-3480
December
2008

論文誌
A. Tsuchiya, M. Hashimoto, H. Onodera
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling
IEICE Trans. on Electronics
E90-C
6
1267-1273
June
2007

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560--3568
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in SoC Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
A. Tsuchiya, M. Hashimoto, H. Onodera
Performance Limitation of On-chip Global Interconnects for High-Speed Signaling
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science
E88-A
4
885-891
April
2005

国際会議
L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, C-K Cheng
High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


385--390
January
2009

国際会議
Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, C.-K. Cheng
On-Chip High Performance Signaling using Passive Compensation
Proceedings of IEEE International Conference on Computer Design (ICCD)


182-187
October
2008

国際会議
M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration
Proc. IEEE Custom Integrated Circuits Conference


869-872
September
2007

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)


227--230
May
2006

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction
The 3rd International Workshop on Compact Modeling


51--56
January
2006

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Interconnect RL Extraction at a Single Representative Frequency
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


515-520
January
2006

国際会議
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
Performance Prediction of On-chip High-throughput Global Signaling
Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)


79-82
October
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)


613-616
September
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Substrate Loss of On-chip Transmission-lines with Power/Ground Wires in Lower Layer
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)


Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)
May
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics
Proceedings of International Meeting for Future of Electron Devices, Kansai


33-34
April
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Return Path Selection for Loop RL Extraction
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


1078-1081
January
2005

国際会議
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
Performance Prediction of On-chip Global Signaling
IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)


87-100
November
2004

国際会議
M. Hashimoto, A. Tsuchiya, H. Onodera
On-Chip Global Signaling by Wave Pipelining
IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)


311-314
October
2004

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Performance Limitation of On-chip Global Interconnects for High-speed Signaling
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)


489-492
September
2004

大会等発表論文
Siriporn Jangsombatsiri, 橋本昌宜, 土谷亮, Haikun Zhu, Chung-Kuan Cheng
シャントコンダクタンスを挿入したオンチップ伝送線路のアイパターン評価
電子情報通信学会総合大会, A-3-9



March
2007


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