著者名 (author) 表題 (title) 論文誌/会議名 巻数 (volume) 号数 (number) ページ範囲 (pages) 刊行月 (month) 出版年 (year) File
論文誌
S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, S. Imai
Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays
IEICE Trans. on Fundamentals
E86-A
12
2923--2932
December
2003

論文誌
B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, I. Shirakawa
Low-Power {VLSI} Implementation by {NMOS} 4-Phase Dynamic Logic
Trans. of IPSJ
41
4
899--907
April
2000

論文誌
松村 謙次, 古家 眞, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘
医療用監視システムとその通信制御用 {LSI} の設計
情報処理学会論文誌
41
4
962--969
April
2000

論文誌
B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, I. Shirakawa
Low-Power Scheme of {NMOS} 4-Phase Dynamic Logic
IEICE Trans. Electron.
E82--C
9
1772--1776
September
1999

国際会議
S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, S. Imai
A Parasitic Capacitance Modeling Method for Non-Planar Interconnects
in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003)


294--299
April
2003

国際会議
S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, S. Imai
Parasitic Capacitance Modeling for Multilevel Interconnects
in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002
1

59--64
December
2002

国際会議
M. Furuie, T. Onoye, S. Tsukiyama, I. Shirakawa
Two-Dimensional Array Layout for {NMOS} 4-Phase Dynamic Logic
in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta


589--592
September
2001

国際会議
R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, I. Shirakawa
Realtime Wavelet Video Coder Based on Reduced Memory Accessing
in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan


15--16
January
2001

国際会議
R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, I. Shirakawa
{VLSI} Implementation of a Realtime Wavelet Video Coder
in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA


543--546
May
2000

国際会議
M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, I. Shirakawa
Layout Generation of Array cell for {NMOS} 4-phase Dynamil Logic
in Proc. ASP-DAC2000


529--532
January
2000

国際会議
M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, I. Shirakawa
Layout Generation for Low-Power {NMOS} 4-Phase Dynamic Logic Array
in Proc. IEEE Region 10 Conference (TENCON '99)


872--875
September
1999

国際会議
B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, I. Shirakawa
Array macro cell architecture for low-power {NMOS} 4-phase dynamic logic
in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan


561--564
July
1999

国際会議
J. Fan, G. Fujita, M. Furuie, T. Onoye, I. Shirakawa
Structual Objeco-Oriented Video Segmentation and Representation Algorithm
in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems


78--82
November
1998

国際会議
M. Furuie, T. Onoye, S. Tsukiyama, Isao Shirakawa
Two-Dimensional Array Layout for Low Power {NMOS} 4-Phase Dynamic Logic
in Proc. International Conference on Electronics Packaging(2001 ICEP), Tokyo, April, 2001.


417--421



研究会等発表論文
古家 眞, 宋 宝玉, 吉田 幸弘, 尾上 孝雄, 白川 功
4相{NMOS}ダイナミックロジック用アレイセル
信学技報, CAS99-62


1--6
September
1999

研究会等発表論文
古家 眞, 松村 謙次, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘
医療用監視システムのための通信制御用{LSI}
信学技報, CAS99


15--19
June
1999


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