著者名 (author) 表題 (title) 論文誌/会議名 巻数 (volume) 号数 (number) ページ範囲 (pages) 刊行月 (month) 出版年 (year) File
論文誌
H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
12
2518--2529
December
2014

論文誌
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
Timing Analysis Considering Temporal Supply Voltage Fluctuation
IEICE Trans. on Information and Systems
E91-D
3
655--660
March
2008

論文誌
M. Hashimoto, J. Yamaguchi, H. Onodera
Timing Analysis Considering Spatial Power/Ground Level Variation
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E90-A
12
2661-2668
December
2007

論文誌
A. Tsuchiya, M. Hashimoto, H. Onodera
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling
IEICE Trans. on Electronics
E90-C
6
1267-1273
June
2007

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560--3568
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in SoC Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
3560-3568
December
2006

論文誌
M. Hashimoto, T. Yamamoto, H. Onodera
Statistical Analysis of Clock Skew Variation in H-tree Structure
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3375-3381
December
2005

論文誌
A. Muramatsu, M. Hashimoto, H. Onodera
Effects of On-chip Inductance on Power Distribution Grid
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3564-3572
December
2005

論文誌
T. Sato, M. Hashimoto, H. Onodera
Successive pad assignment for minimizing supply voltage drop
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A
12
3429-3436
December
2005

論文誌
A. Tsuchiya, M. Hashimoto, H. Onodera
Performance Limitation of On-chip Global Interconnects for High-Speed Signaling
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science
E88-A
4
885-891
April
2005

論文誌
T. Miyazaki, M. Hashimoto, H. Onodera
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and An LC Oscillator Based PLL
IEICE Trans. on Electronics
E88-C
3
437-444
March
2005

論文誌
M. Hashimoto, H. Onodera
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E87-A
12
3251-3257
December
2004

論文誌
M. Hashimoto, Y. Yamada, H. Onodera
Equivalent Waveform Propagation for Static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
23
4
498-508
April
2004

国際会議
R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto
Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)



March
2016

国際会議
N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi Author(s) in English
A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs
Technical Digest of IEEE International Electron Devices Meeting (IEDM)


32--35
December
2015

国際会議
M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, H. Onodera
Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


14--15
January
2015

国際会議
D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)


313-316
November
2013

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)


227--230
May
2006

国際会議
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction
The 3rd International Workshop on Compact Modeling


51--56
January
2006

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Interconnect RL Extraction at a Single Representative Frequency
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


515-520
January
2006

国際会議
T. Kouno, M. Hashimoto, H. Onodera
Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)


453-456
November
2005

国際会議
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
Performance Prediction of On-chip High-throughput Global Signaling
Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)


79-82
October
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)


613-616
September
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Substrate Loss of On-chip Transmission-lines with Power/Ground Wires in Lower Layer
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)


Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)
May
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics
Proceedings of International Meeting for Future of Electron Devices, Kansai


33-34
April
2005

国際会議
A. Muramatsu, M. Hashimoto, H. Onodera
Effects of On-chip Inductance on Power Distribution Grid
Proceedings of International Symposium on Physical Design (ISPD)


63-69
April
2005

国際会議
M. Hashimoto, T. Yamamoto, H. Onodera
Statistical Analysis of Clock Skew Variation in H-tree Structure
Proceedings of International Symposium on Quality Electronic Design (ISQED)


402-407
March
2005

国際会議
T. Sato, M. Hashimoto, H. Onodera
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


723-728
January
2005

国際会議
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
Timing Analysis Considering Temporal Supply Voltage Fluctuation
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


1098-1101
January
2005

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Return Path Selection for Loop RL Extraction
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


1078-1081
January
2005

国際会議
A. Shinmyo, M. Hashimoto, H. Onodera
Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


D9-D10
January
2005

国際会議
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
Performance Prediction of On-chip Global Signaling
IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)


87-100
November
2004

国際会議
M. Hashimoto, J. Yamaguchi, H. Onodera
Timing Analysis Considering Spatial Power/Ground Level Variation
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)


814-820
November
2004

国際会議
M. Hashimoto, A. Tsuchiya, H. Onodera
On-Chip Global Signaling by Wave Pipelining
IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)


311-314
October
2004

国際会議
A. Muramatsu, M. Hashimoto, H. Onodera
LSI Power Network Analysis with On-chip Wire Inductance
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)


55-60
October
2004

国際会議
T. Sato, M. Hashimoto, H. Onodera
An IR-drop minimization by optimizing number and location of power supply pads
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)


66-72
October
2004

国際会議
M. Hashimoto, T. Yamamoto, H. Onodera
Statistical Analysis of Clock Skew Variation
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)


214-219
October
2004

国際会議
T. Miyazaki, M. Hashimoto, H. Onodera
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and An LC Oscillator Based PLL
IEEJ International Analog VLSI Workshop


45-50
October
2004

国際会議
A. Tsuchiya, M. Hashimoto, H. Onodera
Performance Limitation of On-chip Global Interconnects for High-speed Signaling
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)


489-492
September
2004

国際会議
A. Shinmyo, M. Hashimoto, H. Onodera
Design and Optimization of CMOS Current Mode Logic Dividers
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits


434-435
August
2004


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