論文誌

[1] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014.

[2] H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1468--1482, July 2014.

[3] H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Nbti Mitigation Method by Inputting Random Scan-In Vectors in Standby Time," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1483--1491, July 2014.

[4] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10t Subthreshold Sram," IEEE Transactions on Device and Materials Reliability, volume 14, number 1, 463 -- 470, March 2014.

[5] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, volume 21, number 12, 2165 -- 2178, December 2013.

[6] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices," IEICE Trans. on Information and Systems , volume E96-D, number 8, pages 1624--1631, August 2013.

[7] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 20, number 2, pages 333--343, February 2012.

[8] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Trans. Fundamentals, volume E94-A, number 12, pages 2545-2553, December 2011.

[9] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Transactions on Nuclear Science, volume 58, number 4, pages 2097--2102, August 2011.

[10] H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, "An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion," IEEE Transactions on Circuits and Systems II, volume 58, number 5, pages 299--303, May 2011.

[11] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 18, number 7, pages 1118--1129, July 2010.

[12] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3094-3102, December 2009.

[13] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, "Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 92-A, number 4, pages 990--997, April 2009.

[14] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," IEICE Trans. on Electronics, volume E92-C, number 2, pages 281-285, February 2009.

[15] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," IEICE Trans. on Information and Systems , volume E91-D, number 3, pages 655--660, March 2008.

[16] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2661-2668, December 2007.

[17] M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, "Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4," International Journal of Computer Science and Network Security, volume 7, number 7, pages 20-30, July 2007.

[18] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling," IEICE Trans. on Electronics, volume E90-C, number 6, pages 1267-1273, June 2007.

[19] K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, "An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control," In IEEE Trans. Consumer Electronics, volume 53, number 1, pages 124--130, February 2007.

[20] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560--3568, December 2006.

[21] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006.

[22] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006.

[23] G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa, "Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation," In IEICE Trans. Fundamentals, volume E89-A, number 4, pages 941--949, April 2006.

[24] H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, "Design Framework for JPEG2000 System Architecture," In Journal of Intelligent Automation and Soft Computing, volume 13, number 3, pages 331--343, March 2006.

[25] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3375-3381, December 2005.

[26] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3564-3572, December 2005.

[27] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment for Minimizing Supply Voltage Drop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3429-3436, December 2005.

[28] A. Kosaka, H. Okuhata, T. Onoye, and I. Shirawaka, "Desing of Ogg Vorbis Decoder System for Embedded Platform," IEICE Trans. Fundamentals, volume E88-A, number 8, pages 2124--2130, August 2005.

[29] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, volume E88-A, number 4, pages 885-891, April 2005.

[30] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll," IEICE Trans. on Electronics, volume E88-C, number 3, pages 437-444, March 2005.

[31] M. Hashimoto and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E87-A, number 12, pages 3251-3257, December 2004.

[32] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , volume 23, number 4, pages 498-508, April 2004.

[33] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of Java Accelerator for High-Performance Embedded Systems," in IEICE Trans. Fundamentals, volume E86-A, number 12, pages 3079--3088, December 2003.

[34] 宋学燮, 岡田浩行, 藤田玄, 尾上孝雄, 白川功, "MPEG-4動画像符号化におけるバイブリッドエラー隠ぺい方式," 画像電子学 会論文誌, volume 32, number 5, pages 609--620, 2003年9月.

[35] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "Performance Estimation at Architecture Level for Embedded Systems," IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 12, pages 2636--2644, December 2002.

[36] Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, "Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Communications, volume E85-B, number 10, pages 2032--2043, October 2002.

[37] 岡田浩行, 宋学燮, 藤田玄, 尾上孝雄, 白川功, "電子透かしのMPEG-4ビットストリームエラー検出への応用," 画像電子学会誌, volume 31, number 5, pages 900--908, 2002年9月.

[38] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection by Digital Watermarking for MPEG-4 Video Coding," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 6, pages 1281--1288, June 2002.

[39] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "An Architecture of a Matrix-Vector Multiplier Dedicated to Video Decoding and Three-Dimensional Computer Graphics," IEEE Trans. Circuits and Systems for Video Technology, volume 9, number 2, pages 306--314, March 1999.

[40] M. H. Miki, 藤田玄, 尾上孝雄, 白川功, "携帯端末向け低電力 H.263 コーデックコアの VLSI 化設計," 電子情報通信学会論文誌, volume J81-A, number 10, pages 1352--1361, 1998年10月.

[41] H. Okuhata, Morgan H. Miki, T. Onoye, and I. Shirakawa, "A Low-Power DSP Core Architecture for Low Bitrate Speech Codec," IEICE Trans. Fundamentals, volume E81-C, number 8, pages 1616--1621, August 1998.

国際会議

[1] R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.

[2] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi Author(s) in English , "A Novel Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch (2v-1cas) for Nonvolatile Crossbar Switch with Multiple Fan-Outs," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pages 32--35, December 2015.

[3] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015.

[4] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313-316, November 2013.

[5] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.

[6] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures," In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pages 189-194, September 2011.

[7] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability," In IEEE Workshop on Silicon Errors in Logic - System Effects, March 2011.

[8] M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, "VLSI Design of OFDM Baseband Transceiver with Dynamic Spectrum Access," In Proc. of the 18th International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2010), pages 329-332, December 2010.

[9] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," In Proceedings of International Reliability Physics Symposium (IRPS), pages 213--217, May 2010.

[10] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-Bit Risc Processor with 4.18pj/Cycle at 0.5v Operation," In Proceedings of IEEE COOL Chips, page 190, April 2010.

[11] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration," In Proc. International Symposium on Quality Electronic Design (ISQED), pages 646-651, March 2010.

[12] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits," In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pages 361-362, January 2010.

[13] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient Vlsi Architecture for Signal Processing," In Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009.

[14] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits," In Proc. IEEE Custom Integrated Circuits Conference, pages 215-218, September 2009.

[15] R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, "Implementation of Ofdm Baseband Transceiver with Dynamic Spectrum Access for Cognitive Radio Systems," In Proc. of 9th International Symposium on Communication and Information Technology (ISCIT2009), pages 658-663, September 2009.

[16] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 186--192, August 2009.

[17] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability," In Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.

[18] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pages 266-271, January 2009.

[19] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits," In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.

[20] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits," In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 3-8, August 2008.

[21] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -," In ACM Great Lakes Symposium on VLSI, pages 387-390, May 2008.

[22] H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa, "Video Image Enhancement Scheme for High Resolution Consumer Devices," In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP2008), pages 639-644, March 2008.

[23] K. Takahashi, Y. Nozato, H. Okuhata, and T. Onoye, "VLSI Architecture for Real-Time Retinex Video Image Enhancement," In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pages 81--86, October 2007.

[24] K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, "A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pages 233-237, October 2007.

[25] K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, "An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control," In International Conference on Consumer Electronics Digest of Technical Papers, P1-20, January 2007.

[26] J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, "Probabilistic Pedestrian Tracking Based on a Skeleton Model," In Proc. International Conference on Image Processing, pages 2825--2828, October 2006.

[27] F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura, "A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Signification Extra Bits," In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, volume Ⅲ, pages 97--100, July 2006.

[28] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227--230, May 2006.

[29] H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and Y. Nakamura, "Efficient Memory Architecture for JPEG2000 Entropy Codec," In Proc. International Symposium on Circuits and Systems, pages 2881--2884, May 2006.

[30] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction," In The 3rd International Workshop on Compact Modeling, pages 51--56, January 2006.

[31] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect Rl Extraction at a Single Representative Frequency," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 515-520, January 2006.

[32] T. Kouno, M. Hashimoto, and H. Onodera, "Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 453-456, November 2005.

[33] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip High-Throughput Global Signaling," In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 79-82, October 2005.

[34] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 613-616, September 2005.

[35] R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, "High Quality Motion JPEG2000 Coding Scheme Based on the Human Visual System," In Proc. IEEE Int’l Symp. Circuits and Systems, pages 2096--2099, May 2005.

[36] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer," In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), May 2005.

[37] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics," In Proceedings of International Meeting for Future of Electron Devices, Kansai, pages 33-34, April 2005.

[38] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," In Proceedings of International Symposium on Physical Design (ISPD), pages 63-69, April 2005.

[39] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 402-407, March 2005.

[40] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 723-728, January 2005.

[41] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1098-1101, January 2005.

[42] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Return Path Selection for Loop Rl Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1078-1081, January 2005.

[43] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um Cmos Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), D9-D10, January 2005.

[44] R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, "Video Quality Enhancement for Motion JPEG2000 Encoding Based on the Human Visual System," In Proc. IEEE Asia Pacific Conference on Circuits and Systems, pages 1161--1164, December 2004.

[45] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip Global Signaling," In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) , pages 87-100, November 2004.

[46] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 814-820, November 2004.

[47] M. Hashimoto, A. Tsuchiya, and H. Onodera, "On-Chip Global Signaling by Wave Pipelining," In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 311-314, October 2004.

[48] A. Muramatsu, M. Hashimoto, and H. Onodera, "Lsi Power Network Analysis with On-Chip Wire Inductance," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 55-60, October 2004.

[49] T. Sato, M. Hashimoto, and H. Onodera, "An Ir-Drop Minimization by Optimizing Number and Location of Power Supply Pads," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 66-72, October 2004.

[50] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 214-219, October 2004.

[51] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll," In IEEJ International Analog VLSI Workshop, pages 45-50, October 2004.

[52] H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, "Scalable Design Framework for JPEG2000 System Architecture," In Proc. Asia-Pacific Computer Systems Architecture Conference, pages 6--11, September 2004.

[53] J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, "A Scalable Approach for Estimation of Focus of Expansion," In Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pages 6--11, September 2004.

[54] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 489-492, September 2004.

[55] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Optimization of Cmos Current Mode Logic Dividers," In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits , pages 434-435, August 2004.

[56] T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, "Embedded System Implementation of Scalable and Object-Based Video Coding," In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.

[57] H. Sugita, Q.-M. Vu, T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura, "JPEG2000 High-Speed Progressive Decoding Scheme," In Proc. IEEE International Symposium on Circuits and Systems, pages 873--876, May 2004.

[58] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "SoC Design of Ogg Vorbis Decoder Using Embedded Processor," In in Proc. 2004 Computing Frontier Conference, pages 481--487, April 2004.

[59] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Efficient Error Recovery Scheme for MPEG-4 Video Coding," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 2, pages 1328--1331, July 2003.

[60] S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa, "Low Power Ogg Vorbis Decoder by Embedded Processor," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 1, pages 565--568, July 2003.

[61] Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, "Design Framework for JPEG2000 Encoding System Architecture," In Proc. International Symposium on Circuits and Systems, pages 740--743, May 2003.

[62] Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, "Scalable Design Framework for JPEG2000 Encoder Architecture," In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pages 372--376, April 2003.

[63] Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, "Implementation of Wireless MPEG2 Transmission System Using IEEE 802.11b PHY," In ibid, volume 1, pages 39--44, December 2002.

[64] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications," In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pages 20--24, September 2002.

[65] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor," In in Proc. 17th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), Phuket, Thailand, pages 94--97, July 2002.

[66] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Digital Watermark Based Error Detection for MPEG-4 Bitstream Error," In ibid, pages 152--155, July 2002.

[67] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Hybrid Error Concealment Algorithm for MPEG-4 Videodecoders," In ibid, pages 611--614, July 2002.

[68] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "Power Estimation at Architecture Level for Embedded Systems," In ibid, volume II, pages 476--479, May 2002.

[69] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "A Java Accelerator for High Performance Embedded Systems," In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.

[70] M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, "High Performance Java Hardware Engine and Software Kernel for Embedded Systems," In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pages 365--369, December 2001.

[71] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "An Architecture Level Power Estimation Method for Embedded Systems," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 78--85, October 2001.

[72] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "High Performance Java Execution for Embedded Systems," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 346--350, October 2001.

[73] H. Okada, H. S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection Based on Check Marker Embedding for MPEG-4 Video Coding," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 96--99, July 2001.

[74] H. S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Error Concealment Algorithm by Motion Estimation Method for MPEG-4 Video Decoder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 104--107, July 2001.

[75] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "Realtime Wavelet Video Coder Based on Reduced Memory Accessing," In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pages 15--16, January 2001.

[76] S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa, "VLSI Implementation of Portable MPEG-4 Audio Decoder," In in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA, pages 80--84, September 2000.

[77] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of a Realtime Wavelet Video Coder," In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pages 543--546, May 2000.

[78] M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, "Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, volume IV, pages 572--575, June 1999.

[79] H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, "Hybrid Media-Processor Core for Natural and Synthetic Video Decoding," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, volume IV, pages 275--278, June 1999.

[80] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Low-Power Architecture of H.324 Codec Dedicated to Mobile Computing," In in Proc. EUROMEDIA'99 , Munich, Germany, pages 145--149, April 1999.

[81] K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, "Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware," In in Proc. IEEE Internatinal Solid-State Circuits Conference, pages 106--107, February 1999.

[82] H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, "Hybrid VLSI Architecture for Motion Compensation and Texture Mapping," In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pages 383--386, November 1998.

[83] H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura, "Matrix-Vector Multiplier Module for Natural/Synthetic Hybrid Video Coding," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pages 631--634, November 1998.

[84] Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and I. Shirakawa, "VLSI Implementation of Function Module for Texture Mapping and Motion Compensation," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 179--182, July 1998.

[85] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "Matrix-Vector Multiplier for Natural/Synthetic Hybrid Video Coding," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1269--1272, July 1998.

[86] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of H.324 Audiovisual Codec for Mobile Computing," In in Proc. IEEE Custom Integrated Circuits Conference, pages 193--196, May 1998.

[87] H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "A Low Power DSP Core Architecture for Low Bitrate Speech Codec," In in Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal Processing, pages 3121--3124, May 1998.

[88] T. Onoye, G. Fujita, H. Okuhata, M. H. Miki, and I. Shirakawa, "Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing," In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pages 589-594, February 1998.

[89] H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi, "A Unified Media-Processor Architecure for Video Coding and Computer Graphics," In in Proc. International Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional Imaging, pages 253-256, September 1997.

[90] M. H. Miki, G.Fujita, T. Onoye, and I. Sirakawa, "Low-Power H.263 Video CoDec Dedicated to Mobile Computing," In in Proc. International Symposium on Low Power Electronics and Design, pages 80-83, August 1997.

[91] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "An Object Code Compression Approach to Embedded Processors," In in Proc. International Symposium on Low Power Electronics and Design, pages 265-268, August 1997.

[92] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "Media-Processor Architecture Unified for Video Coding and 3D Graphics," In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pages 1223-1226, July 1997.

[93] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "Low-Power Consumption Architecture for Embedded Processor," In in Proc. 2nd International Conference on ASIC, pages 77-80, October 1996.

[94] G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa, "Single Chip MPEG2 MP@ML Motion Estimator," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 286-289, July 1996.

[95] N. Shimizu, Y. Mizuta, H. Kondo, and H. Ono, "A New GPS Real-Time Monitoring System for Deformation Measurements and Its Application," In in Proc. 8th FIG Int. Symp. Deformation Measurements, Hong Kong, S1.5, pages 47-54, June 1996.

[96] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@HL," In in Proc. IEEE Custom Integrated Circuits Conference, pages 351-354, May 1996.

[97] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "A VLSI Architecture of MPEG2 MP@HL Motion Estimator," In in Proc. IEEE Int'l Symposium on Circuits and Systems, pages 664-667, May 1996.

研究会等発表論文

[1] 亀田敏広, 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "スキャンパスを用いたＮＢＴＩ劣化抑制に関する研究," 情報処理学会DAシンポジウム, pages 201-206, 2011年8月.

[2] 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "NBTI による劣化予測におけるトランジスタ動作確率算出法の評価," 情報処理学会DAシンポジウム, pages 181-186, 2009年8月.

[3] 宋学燮, Alten-Erdene Shiitev, 岡田浩行, 藤田玄, 尾上孝雄, 白川功, "MPEG-4ビデオ符号化におけるエラー隠蔽アルゴリズムの提案," 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pages 95--100, 2002年4月.

[4] 宋学燮, Altan-Erdene Shiitev, 岡田浩行, 藤田玄, 尾上孝雄, 白川功, "MPEG-4 ビデオ伝送に対するエラー隠蔽アルゴリズムおよびアーキテクチャ," 信学技報, CAS2001-10, pages 71--77, 2001年6月.

[5] 宋天, 宋学燮, 藤田玄, 尾上孝雄, 白川功, "H.263 Version2 コーデックコアの VLSI 化設計," 信学会 第14回回路とシステム(軽井沢)ワークショップ, pages 561--566, 2001年4月.

[6] 宋学燮, 宋天, 岡田浩行, 藤田玄, 尾上孝雄, 白川功, "動き検出を利用した MPEG-4 ビデオにおけるエラー隠蔽アルゴリズムの提案," 信学技報, DSP2000-107, pages 37--43, 2000年10月.

[7] 宋天, 宋学燮, 藤田玄, 尾上孝雄, 白川功, "H.263 拡張 INTRA 符号化モードのコーデックとその VLSI とその VLSI アーキテクチャ," 信学技報, DSP2000-108, pages 45--50, 2000年10月.

[8] 滝大輔, M.H. Miki, 藤田玄, 尾上孝雄, 白川功, 藤原融, 嵩忠雄, "再帰的最尤復号アルゴリズムを用いた誤り訂正復号器の VLSI 設計," 信学技報, VLD98-52, pages 57--62, 1998年9月.

大会等発表論文

[1] Altan-Erdene Shiitev, 岡田浩行, 宋学燮, 藤田玄, 尾上孝雄, 白川功, "電子透かしを用いた MPEG-4 ビデオ伝送におけるエラー検出方式の検討," 信学会 ソサイエティ大会, D-11-38, 2001年9月.

[2] 岡田浩行, 宋学燮, 藤田玄, 尾上孝雄, 白川功, "MPEG-4 ビデオ符号化における電子透かしを利用したエラー検出方式," 2001 画像電子学会年次大会一般セッション, pages 19--20, 2001年6月.