論文誌

[1] M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, "Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes," IEICE Trans. Fundamentals, volume E83-A, number 12, pages 2456--2463, December 2000.

[2] M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, volume E80-A, number 10, pages 1853-1860, October 1997.

国際会議

[1] Y.Fukuhara, A.Yamada, and T.Onoye, "An Image Compression Method for Frame Memory Size Reduction Using Local Feature of Images," In The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2013), pages 288-289, October 2013.

[2] S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa, "C-Based Hardware Design of IMDCT Accelerator for Ogg Vorbis Decoder," In in Proc.12th European Signal Processing Conference (EUSIPCO 2004), pages 1361--1364, September 2004.

[3] M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, "Thread Partitioning Method for Hardware Compiler Bach," In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2000), pages 303--308, January 2000.

[4] M.Yamaguchi, T. Nakaoka, A. Yamada, and T. Kambe, "An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint," In in Proc. IEEE International Symposium on Circuits and Systems, pages 1584-1587, June 1997.

[5] M. Yamaguchi, A. Yamada, T. Nakaoka, and T. Kambe, "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint," In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pages 503-508, January 1997.