論文誌
[1]  続毅海, 伊藤雄一, 安藤正宏, 細井俊輝, 高嶋和毅, 尾上孝雄, 北村喜文, ``StackBlock: 積み重ね形状を認識するブロック型UI,'' 情報処理学会論文誌, vol. 57, no. 12, pp. 2565-2576, December 2016.
[2]  辻本祐輝, 伊藤雄一, 尾上孝雄, ``Ketsuro-Graffiti: 結露を用いたインタラクティブディスプレイ,'' 日本バーチャルリアリティ学会論文誌, vol. 21, no. 3, pp. 513-520, September 2016.
[3]  C. Siriteanu, A. Takemura, C. Koutschan, S. Kuriki, D. Richards, and H. Shin, ``Exact Zf Analysis and Computer-Algebra-Aided Evaluation in Rank-1 Los Rician Fading,'' IEEE Transactions on Wireless Communications, accepted, April 2016.
[4]  Constantin Siriteanu, Satoshi Kuriki, Donald Richards, and Akimichi Takemura, ``Chi-Square Mixture Representations for the Distribution of the Scalar Schur Complement in a Noncentral Wishart Matrix,'' Statistics and Probability Letters, accepted, February 2016.
[5]  S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, ``Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E98-A, no. 12, pp. 2607--2613, December 2015.
[6]  Kosuke TOMITA, Masahide HATANAKA, and Takao ONOYE, ``Implementation of Viterbi Decoder Toward GPU-Based SDR Receiver,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E98-A, no. 11, pp. 2246-2253, November 2015.
[7]  T.T. Oo, T. Onoye, and K. Shin, ``Partial Encryption Method That Enhances MP3 Security,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E98-A, no. 8, pp. 1760-1768, August 2015.
[8]  D. Fukuda, K. Watanabe, Y. Kanazawa, and M. Hashimoto, ``Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E98-A, no. 7, pp. 1467--1474, July 2015.
[9]  T. Shinada, M. Hashimoto, and T. Onoye, ``Proximity Distance Estimation Based on Electric Field Communication between 1mm³ Sensor Nodes,'' Analog Integrated Circuits and Signal Processing, May 2015.
[10]  C.Siriteanu, A.Takemura, S.Kuriki, and H.Shin, ``Mimo Zero-Forcing Performance Evaluation Using the Holonomic Gradient Method,'' IEEE Transactions on Wireless Communications, vol. 14, no. 4, p. 2322 - 2335, April 2015.
[11]  C.Siriteanu, A.Takemura, S.Kuriki, D.Richards, and H.Shin, ``Schur Complement Based Analysis of Mimo Zero-Forcing for Rician Fading,'' IEEE Transactions on Wireless Communications, vol. 14, no. 4, pp. 1757-1771, April 2015.
[12]  S. Hirokawa, R. Harada, M. Hashimoto, and T. Onoye, ``Characterizing Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4-V Srams,'' IEEE Transactions on Nuclear Science, April 2015.
[13]  H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518--2529, December 2014.
[14]  T. Amaki, M. Hashimoto, and T. Onoye, ``A Process and Temperature Tolerant Oscillator-Based True Random Number Generator,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2393--2399, December 2014.
[15]  D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, and M. Hashimoto, ``Edge-Over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2373--2382, December 2014.
[16]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Exploring Well-Configurations for Minimizing Single Event Latchup,'' IEEE Transactions on Nuclear Science, vol. 61, no. 6, pp. 3282--3289, December 2014.
[17]  H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1468--1482, July 2014.
[18]  H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Nbti Mitigation Method by Inputting Random Scan-In Vectors in Standby Time,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1483--1491, July 2014.
[19]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1461--1467, July 2014.
[20]  遠藤隆介, 伊藤雄一, 中島康祐, 岸野文郎, ``マルチタッチディスプレイを用いた複数人によるプランニングができるデジタルサイネージシステムの提案,'' 情報処理学会論文誌, vol. 55, no. 4, April 2014.
[21]  H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10t Subthreshold Sram,'' IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, p. 463 -- 470, March 2014.
[22]  C.Siriteanu, S.D. Blostein, A.Takemura, H.Shin, S.Yousefi, and S.Kuriki, ``Exact Mimo Zero-Forcing Detection Analysis for Transmit-Correlated Rician Fading,'' IEEE Transactions on Wireless Communications, vol. 13, no. 3, pp. 1514-1527, March 2014.
[23]  Sho Tsugawa, Hiroyuki Ohsaki, Yuichi Itoh, Naonori Ono, Keiichiro Kagawa, and Kazuki Takashima, ``Dynamic Social Network Analysis with Heterogeneous Sensors in Ambient Environment,'' Social Networking, vol. 3, no. 1, pp. 9-18, January 2014.
[24]  D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, vol. 21, no. 12, p. 2165 -- 2178, December 2013.
[25]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4362--4367, December 2013.
[26]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft-Error in Sram at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4232--4237, December 2013.
[27]  M. Okada, M. Hatanaka, K. Kagawa, and S. Miyamoto, ``Realization of Secure Ambient Wireless Network System Based on Spatially Distributed Ciphering Function,'' IEICE Trans. on Fundamentals of Electronics, vol. E96-A, no. 11, November 2013.
[28]  中島康祐, 伊藤雄一, 林勇介, 池田和章, 藤田和之, 尾上孝雄, ``Emoballoon: ソーシャルタッチインタラクションのための柔らかな風船型インタフェース,'' 日本バーチャ ルリアリティ学会論文誌, vol. 18, no. 3, pp. 255-265, September 2013.
[29]  K. Shinkai, M. Hashimoto, and T. Onoye, ``A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations,'' Integration, the VLSI Journal, vol. 46, no. 4, pp. 345--358, September 2013.
[30]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement,'' IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 2630--2634, August 2013.
[31]  T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,'' IEICE Trans. on Information and Systems , vol. E96-D, no. 8, pp. 1624--1631, August 2013.
[32]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling,'' IEEE Transactions on Information Forensics and Security, vol. 8, no. 8, pp. 1331--1342, August 2013.
[33]  Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Supply Noise Suppression by Triple-Well Structure,'' IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp. 781--785, April 2013.
[34]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices,'' IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
[35]  I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, ``A 0.8-V 110-Na Cmos Current Reference Circuit Using Subthreshold Operation,'' IEICE Electronics Express (ELEX), vol. 10, no. 4, March 2013.
[36]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 3, pp. 684--696, March 2013.
[37]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 2, pp. 459--468, February 2013.
[38]  藤田和之, 高嶋和毅, 伊藤雄一, 大崎博之, 小野直亮, 香川景一郎, 津川翔, 中島康祐, 林勇介, 岸野文郎, ``Ambient Suiteを用いたパーティ場面における部屋型会話支援システムの実装と評価,'' 電子情報通信学会論文誌, vol. J96-D, no. 1, pp. 120-132, January 2013.
[39]  Yusuke Hayashi, Yuichi Itoh, Kazuki Takashima, Kazuyuki Fujita, Kosuke Nakajima, and Takao Onoye, ``Cup-Le: Cup-Shaped Tool for Subtly Collecting Information during Conversational Experiment,'' The International Journal of Advanced Computer Science, vol. 3, no. 1, pp. 44-50, January 2013.
[40]  劉載勲, 宮本龍介, 尾上孝雄, ``CoHOG特徴を用いた歩行者検出の確率的サンプリングに基づく高速化,'' 画像電子学会誌, vol. 42, no. 1, pp. 30-40, January 2013.
[41]  中西正洋, 畠中理英, 尾上孝雄, ``家電機器向けユーザインタフェース管理システム,'' 画像電子学会誌, vol. 42, no. 1, pp. 81-88, January 2013.
[42]  M. Hatanaka, T. Homemoto, and T. Onoye, ``Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems,'' VLSI Design, vol. vol. 2013, Article ID 967370, 9 pages, 2013.
[43]  T. Enami, T. Sato, and M. Hashimoto, ``Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2261--2271, December 2012.
[44]  Y. Takai, M. Hashimoto, and T. Onoye, ``Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2220--2225, December 2012.
[45]  S. Kimura, M. Hashimoto, and T. Onoye, ``A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2292--2300, December 2012.
[46]  R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, ``Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 2791--2795, December 2012.
[47]  Ryusuke Endo, Yuichi Itoh, Kosuke Nakajima, Kazuyuki Fujita, Fumio Kishino, ``Digital Signage Supporting Collaborative Route Planning in Real Commercial Establishment,'' ICIC Express Letters, vol. 6, no. 12, pp. 2967-2972, December 2012.
[48]  M. Okada, T. Onoye, and W. Kobayashi, ``A Ray Tracing Simulation of Sound Diffraction Based on the Analytic Secondary Source Model,'' IEEE Trans. Audio, Speech and Language Processing , vol. 20, no. 9, pp. 2448-2460 , November 2012.
[49]  中島康祐, 伊藤雄一, 築谷喬之, 藤田和之, 高嶋和毅, 岸野文郎, ``FuSA2 Touch Display: 大画面毛状マルチタッチディスプレイ,'' 情報処理学会論文誌, vol. 53, no. 3, pp. 1069-1081, March 2012.
[50]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 20, no. 2, pp. 333--343, February 2012.
[51]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating NBTI-Induced Delay Degradation,'' IEICE Trans. Fundamentals, vol. E94-A, no. 12, pp. 2545-2553, December 2011.
[52]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Extracting Device-Parameter Variations with Ro-Based Sensors,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 12, pp. 2537--2544, December 2011.
[53]  T. Okumura and M. Hashimoto, ``Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 10, pp. 1948--1953, October 2011.
[54]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Transactions on Nuclear Science, vol. 58, no. 4, pp. 2097--2102, August 2011.
[55]  H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, ``An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion,'' IEEE Transactions on Circuits and Systems II, vol. 58, no. 5, pp. 299--303, May 2011.
[56]  T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. 93-A, no. 12, pp. 2399-2408, December 2010.
[57]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2417-2423, December 2010.
[58]  S. Ninomiya and M. Hashimoto, ``Accuracy Enhancement of Grid-Based Ssta by Coefficient Interpolation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2441--2446, December 2010.
[59]  T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in Sta under Dynamic Power Supply Noise,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2447--2455, December 2010.
[60]  M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``3D Sound Rendering for Multiple Sound Sources Based on Fuzzy Clustering,'' IEICE Trans. Fundamentals, vol. E93-A, no. 11, pp. 2163-2172, November 2010.
[61]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 18, no. 7, pp. 1118--1129, July 2010.
[62]  密山 幸男, 高橋 一真, 今井 林太郎, 橋本 昌宜, 尾上 孝雄, 白川 功, ``メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現,'' 電子情報通信学会論文誌, vol. J93-A, no. 6, pp. 397-413, June 2010.
[63]  渡邊 賢治, 達可 敏充, 畠中 理英, 尾上 孝雄, ``屋内位置推定システムのための間取り推定手法,'' Journal of Signal Processing, vol. 14, no. 3, pp. 231-242, May 2010.
[64]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Prediction of Self-Heating in Short Intra-Block Wires,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 3, pp. 583-594, March 2010.
[65]  T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, ``Impact of Self-Heating in Wire Interconnection on Timing,'' IEICE Trans. on Electronics, vol. E93-C, no. 3, pp. 388--392, March 2010.
[66]  Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, ``Modeling the Overshooting Effect for Cmos Inverter Delay Analysis in Nanometer Technologies,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 29, no. 2, pp. 250--260, February 2010.
[67]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3094-3102, December 2009.
[68]  T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, ``An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3016--3023, December 2009.
[69]  廣本 正之, 筒井 弘, 越智 裕之, 小佐野 智之, 石川 憲洋, 中村 行宏, ``メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法,'' 情報処理学会論文誌, vol. 50, no. 10, pp. 2532-2542, October 2009.
[70]  A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto, ``Interconnect Modeling: a Physical Design Perspective (Invited),'' IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1840--1851, September 2009.
[71]  畠中 理英, 達可 敏充, 渡邊 賢治, 尾上 孝雄, ``透過減衰を考慮した無線ホームネットワーク向け位置推定,'' 情報処理学会論文誌, vol. 50, no. 8, p. 1835–1844, August 2009.
[72]  Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, and Yukihiro Nakamura, ``Efficient Memory Organization Framework for Jpeg2000 Entropy Codec,'' IEICE Trans. Fundamentals, vol. E92-A, no. 8, pp. 1970-1977, August 2009.
[73]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform,'' IEEE Journal of Solid-State Circuits, vol. 44, no. 6, pp. 1745--1755, June 2009.
[74]  増崎 隆彦, 筒井 弘, 尾上 孝雄, 水野 雄介, 佐々木 元, 中村 行宏, ``シングルタイル JPEG2000 コーデックのシステム構成,'' 画像電子学会誌, vol. 38, no. 3, pp. 296-304, May 2009.
[75]  T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 4, pp. 541-553, April 2009.
[76]  T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, ``Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. 92-A, no. 4, pp. 990--997, April 2009.
[77]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Trans. on Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.
[78]  Takahiko Masuzaki, Hiroshi Tsutsui, Quang Minh Vu, Takao Onoye, and Yukihiro Nakamura, ``JPEG2000 High-Speed SNR Progressive Decoding Scheme,'' International Journal of Computer Science and Network Security, vol. 9, no. 1, pp. 62-68, January 2009.
[79]  Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa, ``Area-Efficient Reconfigurable Architecture for Media Processin,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3651-3662, December 2008.
[80]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3461-3464, December 2008.
[81]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3481-3487, December 2008.
[82]  M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, ``Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3474-3480, December 2008.
[83]  R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, ``Implementation of Multi-Agent Object Attention System Based on Biologically Inspired Attractor Selection,'' IEICE Trans. Fundamentals, vol. E91-A, no. 10, October 2008.
[84]  渡辺 慎吾, 橋本 昌宜, 佐藤寿倫, ``タイミング歩留まり改善を目的とする演算器カスケーディング,'' 情報処理学会論文誌コンピューティングシステム, vol. 1, no. 2, pp. 12--21, August 2008.
[85]  Nobuyuki Iwanaga, Tomoya Matsumura, Akihiro Yoshida, Wataru Kobayashi, and Takao Onoye, ``Embedded System Implementation of Sound Localization in Proximal Region,'' IEICE Trans. Fundamentals, vol. E91-A, no. 3, pp. 763-771, March 2008.
[86]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects,'' IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718-728, March 2008.
[87]  M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' IEICE Trans. on Information and Systems , vol. E91-D, no. 3, pp. 655--660, March 2008.
[88]  高橋真吾, 築山修治, 橋本昌宜, 白川功, ``液晶ディスプレイ用サンプリング回路におけるサンプリングパルスとトランジスタサイズの最適設計手法,'' 電子情報通信学会論文誌A, vol. J91-A, no. 3, pp. 373-382, March 2008.
[89]  M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of LCD Driver Circuit for Technology Migration,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2712--2717, December 2007.
[90]  M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2661-2668, December 2007.
[91]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872, October 2007.
[92]  K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Automatic Filter Design for 3-D Sound Movement in Embedded Applications,'' In Acoustical Science and Technology, vol. 28, no. 4, pp. 219-229, July 2007.
[93]  M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, ``Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4,'' International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.
[94]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling,'' IEICE Trans. on Electronics, vol. E90-C, no. 6, pp. 1267-1273, June 2007.
[95]  宮本 龍介, 劉 載勲, 筒井 弘, 中村 行宏, ``可変ウィンドウ手法に基づく高精度ステレオマッチングプロセッサ,'' 画像電子学会誌, vol. 36, no. 3, pp. 210-218, May 2007.
[96]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect,'' In IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 4, pp. 724--731, April 2007.
[97]  K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Efficient 3-D Sound Movement with Time-Varying Iir Filters,'' In IEICE Trans. Fundamentals, vol. E90-A, no. 3, pp. 618--625, March 2007.
[98]  K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, ``An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control,'' In IEEE Trans. Consumer Electronics, vol. 53, no. 1, pp. 124--130, February 2007.
[99]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538--3545, December 2006.
[100]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560--3568, December 2006.
[101]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538-3545, December 2006.
[102]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[103]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[104]  T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3491-3499, December 2006.
[105]  T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M Hashimoto, ``Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3666-3670, December 2006.
[106]  小谷 章夫, 種村 嘉高, 密山 幸男, 朝井 宣実, 中村 安久, 尾上 孝雄, ``ポテンシャルエネルギーを用いた文字重心位置取得手法,'' 画像電子学会誌, vol. 35, no. 4, pp. 296--305, July 2006.
[107]  内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, ``グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積りの容易化,'' 情報処理学会論文誌, vol. 47, no. 6, pp. 1665--1673, June 2006.
[108]  G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa, ``Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation,'' In IEICE Trans. Fundamentals, vol. E89-A, no. 4, pp. 941--949, April 2006.
[109]  H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Framework for JPEG2000 System Architecture,'' In Journal of Intelligent Automation and Soft Computing, vol. 13, no. 3, pp. 331--343, March 2006.
[110]  Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network,'' IEEE Transactions on Consumer Electronics, vol. 52, no. 1, pp. 81--86, February 2006.
[111]  M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``W-CDMA Channel Codec by Configurable Processors,'' In Intelligent Automation and Soft Computing, vol. 12, no. 3, pp. 317--29, 2006.
[112]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3375-3381, December 2005.
[113]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3564-3572, December 2005.
[114]  T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment for Minimizing Supply Voltage Drop,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3429-3436, December 2005.
[115]  T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3382-3389, December 2005.
[116]  A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, , Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, ``Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3453-3462, December 2005.
[117]  藤田玄, 尾上孝雄, 白川功, ``MPEG-4向け高精度動き検出コアのVLSI化設計,'' 電子情報通信学会論文誌, vol. J88-A, no. 11, pp. 1282-1382, November 2005.
[118]  A. Kosaka, H. Okuhata, T. Onoye, and I. Shirawaka, ``Desing of Ogg Vorbis Decoder System for Embedded Platform,'' IEICE Trans. Fundamentals, vol. E88-A, no. 8, pp. 2124--2130, August 2005.
[119]  K. Tsujino, K. Furuya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, ``Design of Realtime 3-D Sound Processing System,'' In IEICE Trans. Fundamentals, vol. E88-A, no. 8, pp. 2124--2130, August 2005.
[120]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線容量抽出手法,'' 情報処理学会論文誌, vol. 46, no. 6, pp. 1395--1403, June 2005.
[121]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp. 899-906, April 2005.
[122]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E88-A, no. 4, pp. 885-891, April 2005.
[123]  T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' IEICE Trans. on Electronics, vol. E88-C, no. 3, pp. 437-444, March 2005.
[124]  T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function,'' IEEE Transactions on Consumer Electronics, vol. 51, no. 1, pp. 262--267, February 2005.
[125]  M. Hatanaka, T. Masaki, M. Okada, and K. Murakami, ``VLSI Architecture of PSK Demodulator for Digital BS and CS Broadcasting,'' 映像情報メディア学会誌, vol. 59, no. 1, pp. 69--76, January 2005.
[126]  M. Hashimoto and H. Onodera, ``Crosstalk Noise Optimization by Post-Layout Transistor Sizing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E87-A, no. 12, pp. 3251-3257, December 2004.
[127]  M. Hashimoto, Y. Yamada, and H. Onodera, ``Equivalent Waveform Propagation for Static Timing Analysis,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 23, no. 4, pp. 498-508, April 2004.
[128]  岡田 勉, 内田 翼, 尾上 孝雄, 白川 功, ``次世代 GNSS 受信機用信号処理 機構とその VLSI 化設計,'' 電子情報通信学会論文誌, vol. J86-A, no. 12, pp. 1417--1425, December 2003.
[129]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays,'' IEICE Trans. on Fundamentals, vol. E86-A, no. 12, pp. 2923--2932, December 2003.
[130]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``Implementation of Java Accelerator for High-Performance Embedded Systems,'' in IEICE Trans. Fundamentals, vol. E86-A, no. 12, pp. 3079--3088, December 2003.
[131]  宋 学燮, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4動画像符号化におけるバイブリッドエラー隠ぺい方式,'' 画像電子学 会論文誌, vol. 32, no. 5, pp. 609--620, September 2003.
[132]  小谷 章夫, 小山 至幸, 密山 幸男, 尾上 孝雄, ``低解像度表示デバイス向けフォント "LCFONT" の重心位置および可読性評価,'' 画像電子学会誌, vol. 32, no. 5, pp. 621--628, September 2003.
[133]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources,'' in IEEE Trans. on Consumer Electronics, vol. 49, no. 3, pp. 737--741, August 2003.
[134]  T. Okamoto, T. Yuasa, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Tools and Trial Design for Pca-Chip2,'' In IEICE Trans. Information and Systems,, vol. E86-D, no. 5, pp. 868--871, May 2003.
[135]  K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa, ``Object Sharing Scheme for Heterogeneous Environment,'' in IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 4, pp. 813--821, April 2003.
[136]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm,'' Journal of Circuits, Systems and Computers, vol. 12, no. 1, pp. 55-73, February 2003.
[137]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Performance Estimation at Architecture Level for Embedded Systems,'' IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 12, pp. 2636--2644, December 2002.
[138]  Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, ``Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Communications, vol. E85-B, no. 10, pp. 2032--2043, October 2002.
[139]  岡田 浩行, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``電子透かしのMPEG-4ビットストリームエラー検出への応用,'' 画像電子学会誌, vol. 31, no. 5, pp. 900--908, September 2002.
[140]  H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Detection by Digital Watermarking for MPEG-4 Video Coding,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 6, pp. 1281--1288, June 2002.
[141]  宋 天, 藤田 玄, 尾上 孝雄, 白川 功, ``携帯端末用低消費電力 H.263 Version 2 コーデックコアのVLSI化設計,'' 情報処理学会論文誌, vol. 43, no. 4, pp. 1161--1170, May 2002.
[142]  M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, ``Code Efficiency Evaluation for Embedded Processors,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 4, pp. 811--818, April 2002.
[143]  Roberto Y. Omaki, Gen Fujita, Takao Onoye, and Isao Shirakawa, ``An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E85-A, no. 3, pp. 703--713, March 2002.
[144]  Hiroshi Tsutsui, Akihiko Tomita, Shigenori Sugimoto, Kazuhisa Sakai, Tomonori Izumi, Takao Onoye, and Yukihiro Nakamura, ``Lut-Array-Based Pld and Synthesis Approach Based on Sum of Generalized Complex Terms Expression,'' IEICE Trans. Fundamentals, vol. E84-A, no. 11, pp. 2681-2689, November 2001.
[145]  谷 貞宏, 白川 功, ``多層プリント回路板の電源供給系におけるインピーダンスシミュレーション,'' エレクトロニクス実装学会誌, vol. 4, no. 5, pp. 378--385, August 2001.
[146]  W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' IEICE(The Institute of Electronics, Information and Communication Engineers) Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1423--1430, June 2001.
[147]  T. Watanabe and N. Ishiura, ``Resister Constraint Analysis to Minimize Spill Code for Application Specific DSPs,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1541--1544, June 2001.
[148]  K. Kawamoto, K. Kohno, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A 25kV ESD Proof LDMOSFET with a Turn-On Discharge MOSFET,'' IEICE Trans. Electron, vol. E84-C, no. 6, pp. 823--831, June 2001.
[149]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A Novel Dynamically Reconfigurable Hardware-Based Cipher,'' 情報処理学会論文誌, vol. 42, no. 4, pp. 958--966, April 2001.
[150]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, ``A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS,'' The Japan Society of Applied Physics, vol. 40, no. 4B, pp. 2891--2896, April 2001.
[151]  K. Kawamoto, H. Yamaguchi, H. Himi, S. Fujino, and I. Shirakawa, ``A 200 V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays,'' IEICE Trans. Electron, vol. E84-C, no. 2, pp. 260--266, February 2001.
[152]  M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, ``Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes,'' IEICE Trans. Fundamentals, vol. E83-A, no. 12, pp. 2456--2463, December 2000.
[153]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic,'' Trans. of IPSJ, vol. 41, no. 4, pp. 899--907, April 2000.
[154]  松村 謙次, 古家 眞, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘, ``医療用監視システムとその通信制御用 LSI の設計,'' 情報処理学会論文誌, vol. 41, no. 4, pp. 962--969, April 2000.
[155]  M. Hatanaka, T. Masaki, T. Onoye, and K. Murakami, ``VLSI Architecture of Switching Control for AAL Type2 Switch,'' IEICE Trans. Fundamentals, vol. E83--A, no. 3, pp. 435--441, March 2000.
[156]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Scheme of NMOS 4-Phase Dynamic Logic,'' IEICE Trans. Electron., vol. E82--C, no. 9, pp. 1772--1776, September 1999.
[157]  H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``An Architecture of a Matrix-Vector Multiplier Dedicated to Video Decoding and Three-Dimensional Computer Graphics,'' IEEE Trans. Circuits and Systems for Video Technology, vol. 9, no. 2, pp. 306--314, March 1999.
[158]  A. Nagao, I. Shirakawa, and T. Kambe, ``A Layout Approach to Monolithic Microwave IC,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1262--1272, December 1998.
[159]  Masayuki Yamaguchi, Nagisa Ishiura, and Takashi Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal DSP Architecture,'' IEICE Trans. Fundamentals, vol. E81-A, no. 12, pp. 2630--2639, December 1998.
[160]  M. H. Miki, 藤田 玄, 尾上 孝雄, 白川 功, ``携帯端末向け低電力 H.263 コーデックコアの VLSI 化設計,'' 電子情報通信学会論文誌, vol. J81-A, no. 10, pp. 1352--1361, October 1998.
[161]  長尾 明, 澤 卓, 重弘 裕二, 白川 功, 神戸 尚志, ``方形パッキング法の一算法,'' 電子情報通信学会論文誌, vol. J81-A, no. 10, pp. 1362--1371, October 1998.
[162]  H. Okuhata, Morgan H. Miki, T. Onoye, and I. Shirakawa, ``A Low-Power DSP Core Architecture for Low Bitrate Speech Codec,'' IEICE Trans. Fundamentals, vol. E81-C, no. 8, pp. 1616--1621, August 1998.
[163]  木村 浩三, 奥畑 宏之, 尾上 孝雄, 白川 功, 清原 督三, 鷺島 敬之, ``マルチスレッドプロセッサのデータキャッシュ制御方式,'' 映像情報メディア学会誌, vol. 52, no. 5, pp. 742--749, May 1998.
[164]  G. Fujita, T. Onoye, and I. Shirakawa, ``A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding,'' IEICE Trans. Electronics, vol. E81-C, no. 5, pp. 702--707, May 1998.
[165]  T. Masaki, Y. Nakatani, T. Onoye, N. Yamai, and K. Murakami, ``Voice Communication on Multimedia ATM Network Using Shared VCI Cell,'' IEICE Trans. Communications, vol. E81-B, no. 2, pp. 340-346, February 1998.
[166]  I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 12, pp. 2589-2599, December 1997.
[167]  M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1853-1860, October 1997.
[168]  S. Yano and N. Ishiura, ``Embedded Memory Array Testing Using a Scannable Configuration,'' IEICE Trans.\ Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1934-1944, October 1997.
[169]  清水則一, 小山修治, 小野浩, 宮下耕一, 近藤仁志, 水田義明, ``GPS変位モニタリングシステムの連続観測における安定性の検証と計測結果 の処理方法の提案,'' 資源と素材, vol. 113, no. 7, pp. 549-554, July 1997.
[170]  吉田 幸弘, 宋 宝玉, 奥畑 宏之, 尾上 孝雄, 白川 功, ``組み込み用プロセッサの低消費電力化に関する一手法,'' 電子情報通信学会論文誌, vol. J80-A, no. 5, pp. 765-771, May 1997.
[171]  K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication,'' J. Circuits, Systems, and Computers, vol. 7, no. 5, pp. 441-457, May 1997.
[172]  H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, ``A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication,'' J. Circuits, Systems, and Computers, vol. 7, no. 5, pp. 483-494, May 1997.
[173]  T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Voice and Telephony Over ATM for Multimedia Network Using Shared VCI Cell,'' J. Circuits, Systems, and Computers, vol. 7, no. 2, pp. 93-110, April 1997.
[174]  S. Yano, K. Akagi, H. Inohara, and N. Ishiura, ``Application of Full Scan Design to Embedded Memory Arrays,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 3, March 1997.
[175]  H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, ``ASK Digital Demodulation Scheme for Noise Immune Infrared Data Communication,'' ACM Wireless Networks, no. 3, pp. 121-129, 1997.
[176]  K. Okada, S. Morikawa, S. Takeuchi, and I. Shirakawa, ``A High Performance Multiplier and Its Application to an FIR Filter Dedicated to Digital Video Transmission,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E79-A, no. 12, pp. 2106-2111, December 1996.
[177]  矢野政顕, 石浦菜岐佐, ``メモリアレーを含む順序回路へのスキャンパス 方式適用,'' 電子情報通信学会論文誌, vol. J79-D-I, no. 12, pp. 1055-1062, December 1996.
[178]  近藤仁志, M. E. Cannon, 清水則一, 中川浩二, ``GPSによる地盤変位モニタリングシステムの開発,'' 土木学会論文誌, no. 546/VI-32, pp. 157-168, September 1996.
[179]  Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``Automatic Layout Recycling Based on Layout Description and Linear Programming,'' in Proc. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp. 959-967, August 1996.
[180]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai, ``Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@{hl},'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E79-A, no. 8, pp. 1210-1216, August 1996.
国際会議
[1]  Yuki Tsujimoto, Yuichi Itoh, and Takao Onoye, ``Ketsuro-Graffiti: an Interactive Dislplay with Water Condensation,'' In Proceedings of ACM International Conference on Interactive Surfaces and Spaces 2016 (ISS 2016), pp. 49-55, November 2016.
[2]  Y. Masuda, M. Hashimoto, and T. Onoye, ``Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 28-35, March 2016.
[3]  R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, ``Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
[4]  U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, and B. Li, ``Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited),'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 705--711, January 2016.
[5]  N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi Author(s) in English , ``A Novel Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch (2v-1cas) for Nonvolatile Crossbar Switch with Multiple Fan-Outs,'' Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 32--35, December 2015.
[6]  Y. Masuda, M. Hashimoto, and T. Onoye, ``Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise,'' In Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 315-322, November 2015.
[7]  R. Doi, M. Hashimoto, and T. Onoye, ``An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication,'' IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), November 2015.
[8]  E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, ``Design of Generic Hardware for Soft Cascade-Based Linear Svm Classification,'' In International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 257-262, November 2015.
[9]  S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, ``Stochastic Timing Error Rate Estimation under Process and Temporal Variations,'' In Proceedings of International Test Conference (ITC), October 2015.
[10]  Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, and M. Hashimoto, ``A Wireless Power Transfer System for Small-Sized Sensor Applications,'' Proceedings of International Conference on Solid State Devices and Materials (SSDM), pp. 154--155, September 2015.
[11]  S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, ``Neutron-Induced Seu and Mcu Rate Characterization and Analysis of Sotb and Bulk Srams at 0.3v Operation,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.
[12]  M. Ueno, M. Hashimoto, and T. Onoye, ``Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization,'' Proceedings of International On-Line Testing Symposium (IOLTS), pp. 188--193, July 2015.
[13]  M. Hashimoto, ``Run-Time Performance Adaptation: Opportunities and Challenges (Invited),'' Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), June 2015.
[14]  T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, ``Impact of Package on Neutron Induced Single Event Upset in 20 Nm Sram,'' Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.
[15]  T. Uemura and M. Hashimoto, ``Investigation of Single Event Upset and Total Ionizing Dose in Feram for Medical Electronic Tag,'' Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.
[16]  T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft Error Immune Latch Design for 20 Nm Bulk Cmos,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2015.
[17]  S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, and T. Onoye, ``3d Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method,'' Proceedings of Virtual Reality Conference (VR), March 2015.
[18]  S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, ``Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 731--736, January 2015.
[19]  M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 14--15, January 2015.
[20]  T. Amaki, M. Hashimoto, and T. Onoye, ``An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 4--5, January 2015.
[21]  Yuki Tsujimoto, Yuichi Itoh, and Takao Onoye, ``Ketsuro-Graffiti: a Canvas with Computer Generated Water Condensation,'' In SIGGRAPH Asia 2015 Emerging Technologies, pp. 15:1--15:2, 2015.
[22]  M. Hashimoto, ``Stochastic Verification of Run-Time Performance Adaptation with Field Delay Testing (Invited),'' Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 751--754, November 2014.
[23]  M. Hashimoto, ``Opportunities and Verification Challenges of Run-Time Performance Adaptation (Invited),'' Proceedings of Asian Test Symposium (ATS), pp. 248--253, November 2014.
[24]  Yohei Miyazaki, Yuichi Itoh, Yuki Tsujimoto, Masahiro Ando, and Takao Onoye, ``Ketsuro-Graffiti: Water Condensation Display,'' In ACE '14 Proceedings of the 11th Conference on Advances in Computer Entertainment Technology, November 2014.
[25]  Kosuke Tomita, Masahide Hatanaka, and Takao Onoye, ``An Approach to GPU Implementation of OFDM Transceiver Using Dynamic Spectrum Access,'' In 2014 International Workshop on Smart Info-Media Systems in Asia, SISA 2014, October 2014.
[26]  M. Hashimoto, ``Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective (Invited),'' Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2014.
[27]  A. Iokibe, M. Hashimoto, and T. Onoye, ``Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground,'' Proceedings of International Conference on Sensing Technology (ICST), pp. 188--193, September 2014.
[28]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Optimizing Well-Configuration for Minimizing Single Event Latchup,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[29]  R. Harada, S. Hirokawa, and M. Hashimoto, ``Measurement of Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4 V Srams,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[30]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, ``Preventing Single Event Latchup with Deep P-Well on P-Substrate,'' Proceedings of International Reliability Physics Symposium (IRPS), June 2014.
[31]  M. Ueno, M. Hashimoto, and T. Onoye, ``Trace-Based Fault Localization with Supply Voltage Sensor,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2014.
[32]  C.Siriteanu, A.Takemura, S.D. Blostein, S.Kuriki, and H.Shin, ``Convergence Analysis of Performance-Measure Expressions for Mimo Zf under Rician Fading,'' Australian Communications Theory Workshop, AUSCTW'14, Sydney, Australia, pp. 114-119 , February 2014.
[33]  Masahiro Ando, Yuichi Itoh, Toshiki Hosoi, Kazuki Takashima, Kosuke Nakajima, and Yoshifumi Kitamura, ``Stackblock: Block-Shaped Interface for Flexible Stacking,'' In Proc. of UIST, pp. 41-42, 2014.
[34]  Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, and Takao Onoye, ``Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design,'' In ReConFig, December 2013.
[35]  D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 313-316, November 2013.
[36]  T. Amaki, M. Hashimoto, and T. Onoye, ``A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction,'' In Proceedings of Asian Solid-State Circuits Conference (A-SSCC), pp. 133-136, November 2013.
[37]  S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, ``Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 107-114, November 2013. (San Jose)
[38]  Kosuke Nakajima, Yuichi Itoh, Yusuke Hayashi, Kazuaki Ikeda, Kazuyuki Fujita, and Takao Onoye, ``Emoballoon: a Balloon-Shaped Interface Recognizing Social Touch Interactions,'' In Proceedings of 10th International Conference on Advances in Computer Entertainment Technology, pp. 182-197, November 2013.
[39]  J. Kono, M. Hashimoto, and T. Onoye, ``Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm^3 Antenna,'' Proceedings of Asia-Pacific Microwave Conference (APMC), pp. 1121--1123, November 2013.
[40]  R. Harada, M. Hashimoto, and T. Onoye, ``Nbti Characterization Using Pulse-Width Modulation,'' IEEE/ACM Workshop on Variability Modeling and Characterization, November 2013.
[41]  Simon Voelker, Kosuke Nakajima, Christian Thoresen, Yuichi Itoh, Kjell Ivar Øvergård, and Jan Borchers, ``Pucs: Detecting Transparent, Passive Untouched Capacitive Widgets on UnmodifiEd Multi-Touch Displays,'' In Adjunct Publication of the 26th Annual ACM Symposium on User Interface Software and Technology, pp. 1-2, October 2013.
[42]  Simon Voelker, Kosuke Nakajima, Christian Thoresen, Yuichi Itoh, Kjell Ivar Øvergård, and Jan Borchers, ``Pucs Demo: Detecting Transparent, Passive Untouched Capacitive Widgets,'' In Proceedings of the 2013 ACM International Conference on Interactive Tabletops and Surfaces, pp. 325-328, October 2013.
[43]  Simon Voelker, Kosuke Nakajima, Christian Thoresen, Yuichi Itoh, Kjell Ivar Øvergård, and Jan Borchers, ``Pucs: Detecting Transparent, Passive Untouched Capacitive Widgets on UnmodifiEd Multi-Touch Displays,'' In Proceedings of the 2013 ACM International Conference on Interactive Tabletops and Surfaces, pp. 101-104, October 2013.
[44]  M. Hashimoto, ``Soft Error Immunity of Subthreshold Sram (Invited),'' Proceedings of IEEE International Conference on ASIC, pp. 91--94, October 2013.
[45]  Y.Fukuhara, A.Yamada, and T.Onoye, ``An Image Compression Method for Frame Memory Size Reduction Using Local Feature of Images,'' In The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2013), pp. 288-289, October 2013.
[46]  Yohei Kojima, Kazuma Aoyama, Yuichi Itoh, Kazuyuki Fujita, Taku Fujimoto, and Kosuke Nakajima, ``Polka Dot: the Garden of Water Spirits,'' In ACM SIGGRAPH 2013 Posters, July 2013. (Article No. 47)
[47]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Scaling Trend of Sram and Ff of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk Cmos Technology,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[48]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft-Error in Sram at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[49]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[50]  T. Shinada, M. Hashimoto, and T. Onoye, ``Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes,'' Proceedings of International NEWCAS Conference, June 2013.
[51]  M. Ueno, M. Hashimoto, and T. Onoye, ``Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures,'' Proceedings of Reconfigurable Architectures Workshop (RAW), pp. 301--305, May 2013.
[52]  Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, and S. Nassif, ``Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator,'' Proceedings of IEEE European Test Symposium (ETS), pp. 106--111, May 2013.
[53]  Kazuyuki Fujita, Yuichi Itoh, Kazuki Takashima, Kosuke Nakajima, Yusuke Hayashi, and Fumio Kishino, ``Ambient Party Room: a Room-Shaped System Enhancing Communication for Parties Or Gatherings,'' In Proceedings of the 2nd International Workshop on Ambient Information Technologies, pp. 1-4, March 2013.
[54]  Kosuke Nakajima, Yuichi Itoh, Yusuke Hayashi, Kazuaki Ikeda, Kazuyuki Fujita, and Takao Onoye, ``Emoballoon: a Balloon-Shaped Interface Recognizing Social Touch Interactions,'' In Proceedings of the 2nd International Workshop on Ambient Information Technologies, pp. 13-16, March 2013.
[55]  M. Hashimoto, ``Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (Invited),'' China Semiconductor Technology International Conference (CSTIC), pp. 1079--1084, March 2013.
[56]  Jin Kono, Masanori Hashimoto, Takao Onoye, ``Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm3 Antenna,'' Microwave Conference Proceedings (APMC), 2013 Asia-Pacific, pp. 1121-1123, 2013.
[57]  Yohei Kojima, Yuichi Itoh, Taku Fujimoto, and Kosuke Nakajima, ``Polka Dot – the Garden of Water Spirits,'' In SIGGRAPH Asia 2013 Emerging Technologies, p. 15, 2013.
[58]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices,'' Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012.
[59]  Yuya Iwasaki, Masahide Hatanaka, and Takao Onoye, ``Performance Improvement of Channel Estimation for Ofdm Baseband Transceiver with Dynamic Subcarrier Selection,'' In The First Asian Conference on Information Systems,ACIS 2012, December 2012.
[60]  Kazutaka Takeuchi, Ryusuke Miyamoto, and Takao Onoye, ``High-Speed Multiview Video Decoding for Embedded System,'' In The First Asian Conference on Information Systems, ACIS 2012, December 2012.
[61]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Converter Based on Minimax Sampling,'' Proceedings of International SoC Design Conference (ISOCC), p. 120 -- 123 , November 2012.
[62]  Kazuki Takashima, Yusuke Hayashi, Kosuke Nakajima, and Yuichi Itoh, ``Cup-Embedded Information Device for Supporting Interpersonal Communication,'' In Proceedings of Joint Virtual Reality Conference of ICAT, EGVE and EuroVR, pp. 19-20, October 2012.
[63]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of Nbti-­Induced Pulse-Width Modulation on Set Pulse-Width Measurement,'' Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.
[64]  T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.
[65]  Ryusuke Endo, Yuichi Itoh, Kosuke Nakajima, Kazuyuki Fujita, and Fumio Kishino, ``Planning-Capable Digital Signage System Using Multi-Touch Display,'' In Proceedings of The 10th Asia Pacific Conference on Computer Human Interaction (APCHI2012), vol. 2, pp. 545-554, August 2012.
[66]  Kosuke Nakajima, Yuichi Itoh, Yusuke Hayashi, Kazuaki Ikeda, Kazuyuki Fujita, and Takao Onoye, ``Emoballoon,'' In Proceedings of The 10th Asia Pacific Conference on Computer Human Interaction (APCHI2012), vol. 2, pp. 681-682, August 2012.
[67]  R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, ``Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Nuclear and Space Radiation Effects Conference, July 2012.
[68]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2012.
[69]  K. Kiyokawa, M. Hatanaka, K. Hosoda, M. Okada, H. Shigeta, Y. Ishihara, F. Ooshita, H. Kakugawa, S. Kurihara, and K. Moriyama, ``Owens Luis - a Context-Aware Multi-Modal Smart Office Chair in an Ambient Environment,'' In The 1st International Workshop on Ambient Information Technologies (AMBIT-2012), Orange County, CA, USA, March 2012.
[70]  H. Shigeta, J. Nakase, Y. Tsunematsu, K. Kiyokawa, M. Hatanaka, K. Hosoda, M. Okada, Y. Ishihara, F. Ooshita, H. Kakugawa, S. Kurihara, and K. Moriyama, ``Implementation of a Smart Office System in an Ambient Environment,'' In The 1st International Workshop on Ambient Information Technologies (AMBIT-2012), Orange County, CA, USA, March 2012.
[71]  K. Watanabe, G. Fujita, T. Homemoto, and R. Hashimoto, ``A High-Speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator,'' The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 6-10, March 2012.
[72]  Kosuke Nakajima, Yuichi Itoh, Takayuki Tsukitani, Kazuyuki Fujita, Kazuki Takashima, Yoshifumi Kitamura, and Fumio Kishino, ``Fusa2 Touch Display: Furry and Scalable Multi-Touch Display,'' In Proceedings of The 1st International Workshop on Ambient Information Technologies, pp. 35-36, March 2012.
[73]  Yusuke Hayashi, Yuichi Itoh, Kazuki Takashima, Kazuyuki Fujita, Kosuke Nakajima, Ikuo Daibo, and Takao Onoye, ``Cup-Le: a Cup-Shaped Device for Conversational Experiment,'' In Proceedings of the 1st International Workshop on Ambient Information Technologies, pp. 36-37, March 2012.
[74]  Kazuyuki Fujita, Yuichi Itoh, Hiroyuki Ohsaki, Naoaki Ono, Keiichiro Kagawa, Kazuki Takashima, Sho Tsugawa, and Kosuke Nakajima, ``Ambient Suite: Room- Shaped Information Environment for Interpersonal Communication,'' In Proceedings of the 1st International Workshop on Ambient Information Technologies, pp. 18-21, March 2012.
[75]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 283--289, February 2012.
[76]  Takashi Nakamae, Akihisa Yamada, Masayuki Yamaguchi, and Takao Onoye, ``A Near-Lossless Image Compression Method Using Adaptive Variable Length Coding,'' In International Conference on Embedded Systems and Intelligent Technology, January 2012.
[77]  K. Kiyokawa, M. Hatanaka, K. Hosoda, M. Okada, H. Shigeta, Y. Ishihara, F. Ooshita, H. Kakugawa, S. Kurihara, and K. Moriyama, ``Owens Luis - a Proposal of a Smart Office Chair in an Ambient Environment,'' In The 21st International Conference on Artificial Reality and Telexistence (ICAT 2011), Osaka, Japan, November 2011.
[78]  Kazuyuki Fujita, Yuichi Itoh, Hiroyuki Ohsaki, Naoaki Ono, Keiichiro Kagawa, Kazuki Takashima, Sho Tsugawa, Kosuke Nakajima, Yusuke Hayashi, and Fumio Kishino, ``Ambient Suite: Enhancing Communication among Multiple Participants,'' In Proceedings of the International Conference on Advances in Computer Entertainment Technology , pp. 25:1-25:8, November 2011.
[79]  Kosuke Nakajima, Yuichi Itoh, Takayuki Tsukitani, Kazuyuki Fujita, Kazuki Takashima, Yoshifumi Kitamura, and Fumio Kishino, ``Fusa2 Touch Display: Furry and Scalable Multi-Touch Display,'' In Proceedings of ACM International Conference on Interactive Tabletops and Surfaces 2011, pp. 35-44, November 2011.
[80]  Kosuke Nakajima, Yuichi Itoh, Takayuki Tsukitani, Kazuyuki Fujita, Kazuki Takashima, Yoshifumi Kitamura, and Fumio Kishino, ``Fusa2 Touch Display,'' In Proceedings of ACM International Conference on Interactive Tabletops and Surfaces 2011, November 2011.
[81]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures,'' In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pp. 189-194, September 2011.
[82]  Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, and Takao Onoye, ``Nbti Mitigation by Giving Random Scan-In Vectors during Standby Mode,'' In PATMOS2011, September 2011.
[83]  Y. Takai, M. Hashimoto, and T. Onoye, ``Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2011.
[84]  M. Okada, T. Onoye, and W. Kobayashi, ``A Ray Tracing Simulation of Sound Diffraction Based on Analytic Secondary Source Model,'' In 19th European Signal Processing Conference (EUSIPCO-2011), Barcelona, Spain, pp. 1653-1657, August 2011.
[85]  M. Hashimoto and H. Fuketa, ``Adaptive Performance Compensation with On-Chip Variation Monitoring (Invited),'' In Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.
[86]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' In Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.
[87]  T. Amaki, M. Hashimoto, and T. Onoye, ``An Oscillator-Based True Random Number Generator with Jitter Amplifier,'' In Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2011), pp. 725-728, May 2011.
[88]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing,'' In Proc. International Reliability Physics Symposium (IRPS), April 2011.
[89]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 46--51, April 2011.
[90]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Extracting Device-Parameter Variations with Ro-Based Sensors,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 13--18, March 2011.
[91]  D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability,'' In IEEE Workshop on Silicon Errors in Logic - System Effects, March 2011.
[92]  Tatsuo Maeno, Hiroshi Tsutsui, and Takao Onoye, ``Hardware Implementation of Real-Time Motion Adaptive Deinterlacing Based on Inpainting,'' In International Conference on Embedded Systems and Intelligent Technology, February 2011.
[93]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling,'' In Proc. International Workshop on Information Security Applications (WISA 2010), pp. 107-121, January 2011.
[94]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 81-82, January 2011.
[95]  K. Shinkai and M. Hashimoto, ``Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability,'' In Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 683-688, January 2011.
[96]  M. Hashimoto, ``Run-Time Adaptive Performance Compensation Using On-Chip Sensors (Invited),'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 285--290, January 2011.
[97]  M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, ``VLSI Design of OFDM Baseband Transceiver with Dynamic Spectrum Access,'' In Proc. of the 18th International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2010), pp. 329-332, December 2010.
[98]  Y. Takai, M. Hashimoto, and T. Onoye, ``Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation,'' In Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 213--216, October 2010.
[99]  Hideyuki Nakamura, Hiroshi Tsutsui, and Takao Onoye, ``Motion-Compensated Frame Interpolation Using Feature Tracking and Motion Segmentation,'' In International Workshop on Smart Info-Media Systems in Asia, September 2010.
[100]  T. Okumura and M. Hashimoto, ``Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2010.
[101]  L. M. Handaya, M. Okada, T. Onoye, and W. Kobayashi, ``Improvement of Frontal Localization with Complement of Multiple Delayed Sounds,'' 2010 International Workshop on Information Communication Technology, August 2010.
[102]  K. Shinkai and M. Hashimoto, ``Self-Heating in Nano-Scale Vlsi Interconnects,'' In Proceedings of International Workshop on Information Communication Technology (ICT), pp. S-1-6, August 2010.
[103]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.
[104]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' In Proceedings of International Reliability Physics Symposium (IRPS), pp. 213--217, May 2010.
[105]  Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to Sso,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pp. 19--20, May 2010.
[106]  D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, ``A 16-Bit Risc Processor with 4.18pj/Cycle at 0.5v Operation,'' In Proceedings of IEEE COOL Chips, p. 190, April 2010.
[107]  Yuki Kawamura, Yasutake Manabe, Takao Onoye, Kazuto Ohara, Hiroyuki Okada, and Ikuo Keshi, ``Implementation of Simultaneous Video Decoding on Multicore Processor,'' In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP 2010), March 2010.
[108]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 646-651, March 2010.
[109]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), March 2010.
[110]  T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 41-46, March 2010.
[111]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.
[112]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 361-362, January 2010.
[113]  T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in Sta under Dynamic Power Supply Noise,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), p. 775 -- 780, January 2010.
[114]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Soft Error Resilient Vlsi Architecture for Signal Processing,'' In Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 183--186, December 2009.
[115]  Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, and Yukihiro Nakamura, ``A High-Throughput Pipelined Architecture for JPEG XR Encoding,'' In Proc. of 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia2009) , pp. 9-17, October 2009. (Best Paper Award)
[116]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 215-218, September 2009.
[117]  R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, ``Implementation of Ofdm Baseband Transceiver with Dynamic Spectrum Access for Cognitive Radio Systems,'' In Proc. of 9th International Symposium on Communication and Information Technology (ISCIT2009), pp. 658-663, September 2009.
[118]  S. Ninomiya and M. Hashimoto, ``Enhancement of Grid-Based Spatially-Correlated Variability Modeling for Improving Ssta Accuracy,'' In Proceedings of IEEE International SOC Conference (SOCC), pp. 337--340, September 2009.
[119]  K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits,'' In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 51--56, August 2009.
[120]  D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.
[121]  Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, and Yukihiro Nakamura, ``Dynamic Rate Control for Media Streaming in High-Speed Mobile Networks,'' In Proc. of IEEE Wireless Communications and Networking Conference (WCNC 2009), April 2009.
[122]  M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``An Embedded Sound Localization System for Multiple Sources by Fuzzy Clustering with Spatial Constraints,'' In 2009 International Workshop on Nonlinear Circuits and Signal Processing (NCSP '09), Waikiki, Hawaii, pp. 257-260, March 2009.
[123]  S. Watanabe, M. Hashimoto, and T. Sato, ``A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 401--407, March 2009.
[124]  Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 236--241, March 2009.
[125]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability,'' In Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
[126]  K. Shinkai and M. Hashimoto, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 79-84, February 2009.
[127]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 266-271, January 2009.
[128]  L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, ``High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 385--390, January 2009.
[129]  M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``A 3D Sound Localization Method for Multiple Sound Sources Based on Fuzzy Clustering,'' In 2008 International Workshop on Smart Info-Media Systems in Bangkok (SISB 2008), pp. 133-138, December 2008.
[130]  T. Enami, M. Hashimoto, and T. Sato, ``Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis,'' In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 420-425, November 2008.
[131]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits,'' In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.
[132]  Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, and Yukihiro Nakamura, ``An Architecture of Photo Core Transform in HD Photo Coding System for Embedded Systems of Various Bandwidths,'' In Proc. of 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2008), pp. 1592-1595, November 2008.
[133]  Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 397--400, November 2008.
[134]  Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, ``On-Chip High Performance Signaling Using Passive Compensation,'' In Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 182-187, October 2008.
[135]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits,'' In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, August 2008.
[136]  S. Watanabe, M. Hashimoto, and T. Sato, ``Cascading Dependent Operations for Mitigating Timing Variability,'' In Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008.
[137]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays,'' In In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.
[138]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -,'' In ACM Great Lakes Symposium on VLSI, pp. 387-390, May 2008.
[139]  T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' In Proc. ACM International Symposium on Physical Design, pp. 160-167, April 2008.
[140]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 520-525, March 2008.
[141]  H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa, ``Video Image Enhancement Scheme for High Resolution Consumer Devices,'' In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP2008), pp. 639-644, March 2008.
[142]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification,'' In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108, January 2008.
[143]  L. Zhang, J. Liu, H. Zhu, C-K Cheng, and M. Hashimoto, ``High Performance Current-Mode Differential Logic,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 720--725, January 2008.
[144]  R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, ``VLSI Architecture of H.264 RDO-Based Block Size Decision for 1080 HD,'' In Proc. PCS, November 2007.
[145]  R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, ``Implementation of Object Attention Based on Multi-Agent Attractor Selection,'' In Proc. SISB, November 2007.
[146]  Yasutake Manabe, Junichi Hara, and Takao Onoye, ``Jpm-Based Differential Image Storage Scheme for Image Revision Management System,'' In IIEEJ Image Electronics and Visual Computing Workshop 2007, November 2007.
[147]  K. Takahashi, Y. Nozato, H. Okuhata, and T. Onoye, ``VLSI Architecture for Real-Time Retinex Video Image Enhancement,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 81--86, October 2007.
[148]  K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, ``A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 233-237, October 2007.
[149]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 783-786, September 2007.
[150]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' In Proc. IEEE European Solid-State Device Research Conference, pp. 115-118, September 2007.
[151]  M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, ``Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 869-872, September 2007.
[152]  Mohd Nadzrul Bin Mohd Nor, T. Matsumura, and T. Onoye, ``Direction of Arrival Estimation Improvement of Speech on a Two-Microphone Array,'' In IASTED International Conference on Signal and Image Processing, pp. 576-115, August 2007. (Honolulu, Hawaii, USA)
[153]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Future Prediction of Self-Heating in Short Intra-Block Wires,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 660-665, March 2007.
[154]  K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, ``An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control,'' In International Conference on Consumer Electronics Digest of Technical Papers, P1-20, January 2007.
[155]  R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, ``VLSI Architecture of H.264 Block Size Decision Based on Rate-Distortion Optimization,'' In Proc. ISPACS, pp. 618--621, December 2006.
[156]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 47-53, November 2006.
[157]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects,'' Proc. IEEE International Conference on Computer Design, pp. 70--75, October 2006.
[158]  J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``Probabilistic Pedestrian Tracking Based on a Skeleton Model,'' In Proc. International Conference on Image Processing, pp. 2825--2828, October 2006.
[159]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 721--724, September 2006.
[160]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation,'' In Proc.~IEEE Custom Integrated Circuits Conference, pp. 861--864, September 2006.
[161]  T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of Lcd Driver Circuit for Technology Migration,'' In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), vol. 1, p. I25--I28, July 2006.
[162]  A. Kosaka and T. Onoye, ``Pipeline Processing of Continuous Speech Recognition Algorithm for Embedded System Implementation,'' In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. , pp. 373--376, July 2006.
[163]  F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Signification Extra Bits,'' In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. , pp. 97--100, July 2006.
[164]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227--230, May 2006.
[165]  K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Automated Design of Digital Filters for 3-D Sound Localization in Embedded Applications,'' In Proc. International Conf. Audio, Speech, and Signal Processing (ICASSP2006), p. V.349--V.352, May 2006.
[166]  H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and Y. Nakamura, ``Efficient Memory Architecture for JPEG2000 Entropy Codec,'' In Proc. International Symposium on Circuits and Systems, pp. 2881--2884, May 2006.
[167]  Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``Domain-Specific Reconfigurable Architecture for Media Processing,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2006), pp. 322--327, April 2006.
[168]  A. Kotani, Y. Tanemura, Y. Mitsuyama, Y. Asai, Y. Nakamura, and T. Onoye, ``Contour-Based Gravity Center Evaluation of Characters,'' In Proc. EUROMEDIA, pp. 15--20, April 2006.
[169]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 59-64, February 2006.
[170]  Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network,'' In International Conference on Consumer Electronics(ICCE2006), digest of technical papers, Las Vegas, Nevada, USA, pp. 391--392, January 2006.
[171]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction,'' In The 3rd International Workshop on Compact Modeling, pp. 51--56, January 2006.
[172]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Interconnect Rl Extraction at a Single Representative Frequency,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 515-520, January 2006.
[173]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, November 2005.
[174]  T. Kouno, M. Hashimoto, and H. Onodera, ``Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 453-456, November 2005.
[175]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip High-Throughput Global Signaling,'' In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 79-82, October 2005.
[176]  79-82, ``Estimation of Maximum Oscillation Frequency for Cmos Lcvcos,'' In Estimation of Maximum Oscillation Frequency for CMOS LCVCOs, October 2005.
[177]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Delay Variation Due to Inductive Coupling,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 305--308, September 2005.
[178]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 613-616, September 2005.
[179]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix Lcd,'' In A Design Scheme for Sampling Switch in Active Matrix LCD, August 2005.
[180]  Huynh Van Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Real-Time Human Object Extraction for Mobile Terminal,'' In in Proc.The 20th Commemorative International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005), Jeju, Korea, vol. 3, pp. 1015-1016, July 2005.
[181]  Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing,'' In Proc. International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC2005), pp. 131--132, July 2005.
[182]  T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai, ``3D Sound Movement System for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2005), Kobe, Japan, pp. 5345-5348, May 2005.
[183]  R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``High Quality Motion JPEG2000 Coding Scheme Based on the Human Visual System,'' In Proc. IEEE Int’l Symp. Circuits and Systems, pp. 2096--2099, May 2005.
[184]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), May 2005.
[185]  Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, ``Interconnect Capacitance Extraction for System LCD Circuits,'' In in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005), pp. 160--163, April 2005.
[186]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics,'' In Proceedings of International Meeting for Future of Electron Devices, Kansai, pp. 33-34, April 2005.
[187]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' In Proceedings of International Symposium on Physical Design (ISPD), pp. 63-69, April 2005.
[188]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 402-407, March 2005.
[189]  T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function,'' In in Proc.~International Conference on Consumer Electronics (ICCE2005), digest of technical papers, Las Vegas, Nevada, USA, 7.1-2, January 2005.
[190]  T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 723-728, January 2005.
[191]  M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1098-1101, January 2005.
[192]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Return Path Selection for Loop Rl Extraction,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1078-1081, January 2005.
[193]  T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1074-1077, January 2005.
[194]  A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um Cmos Process,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), p. D9-D10, January 2005.
[195]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, 1C-03.3, 2005.
[196]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix LCD,'' In Proceedings of European Conference on Circuit Theory and Design, 3e-212, 2005.
[197]  R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``Video Quality Enhancement for Motion JPEG2000 Encoding Based on the Human Visual System,'' In Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 1161--1164, December 2004.
[198]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``VLSI Implementation of 3D Sound Image Movement for Embedded Systems,'' In in Proc. IEEE Region 10 Conference (TENCON) 2004, A--021, November 2004.
[199]  K. Tsujino, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, ``Realtime Filter Redesign for Interactive 3-D Sound Systems,'' In Proc. IEEE Region 10 Conference, pp. 124--127, November 2004.
[200]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip Global Signaling,'' In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) , pp. 87-100, November 2004.
[201]  M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 814-820, November 2004.
[202]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a 3D Sound Movement System,'' In in Proc. The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2004, pp. 121-125, October 2004.
[203]  M. Hashimoto, A. Tsuchiya, and H. Onodera, ``On-Chip Global Signaling by Wave Pipelining,'' In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 311-314, October 2004.
[204]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Lsi Power Network Analysis with On-Chip Wire Inductance,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 55-60, October 2004.
[205]  T. Sato, M. Hashimoto, and H. Onodera, ``An Ir-Drop Minimization by Optimizing Number and Location of Power Supply Pads,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 66-72, October 2004.
[206]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 214-219, October 2004.
[207]  T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' In IEEJ International Analog VLSI Workshop, pp. 45-50, October 2004.
[208]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Embedded Architecture of IEEE802.11i Cipher Algorithms,'' In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pp. 241--246, September 2004.
[209]  S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa, ``C-Based Hardware Design of IMDCT Accelerator for Ogg Vorbis Decoder,'' In in Proc.12th European Signal Processing Conference (EUSIPCO 2004), pp. 1361--1364, September 2004.
[210]  H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, ``Scalable Design Framework for JPEG2000 System Architecture,'' In Proc. Asia-Pacific Computer Systems Architecture Conference, pp. 6--11, September 2004.
[211]  J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A Scalable Approach for Estimation of Focus of Expansion,'' In Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pp. 6--11, September 2004.
[212]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 489-492, September 2004.
[213]  A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Optimization of Cmos Current Mode Logic Dividers,'' In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits , pp. 434-435, August 2004.
[214]  Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa, ``Architecture of Turbo Decoder for W-CDMA by Configurable Processor,'' In Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4, p. 7, July 2004.
[215]  T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, ``Embedded System Implementation of Scalable and Object-Based Video Coding,'' In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.
[216]  H. Sugita, Q.-M. Vu, T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura, ``JPEG2000 High-Speed Progressive Decoding Scheme,'' In Proc. IEEE International Symposium on Circuits and Systems, pp. 873--876, May 2004.
[217]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``SoC Design of Ogg Vorbis Decoder Using Embedded Processor,'' In in Proc. 2004 Computing Frontier Conference, pp. 481--487, April 2004.
[218]  K. Tsujino, A. Shigiya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, ``An Implementation of Moving 3-D Sound Synthesis System Based on Floating Point Dsp,'' In Proc. IEEE International Symposium on Signal Processing and Information Technology, pp. WA4-8.1-WA4-8.4, December 2003.
[219]  K. Tsujino, A. Shigiya, T. Izumi, T. Onoye, Y. Nakamura, and W. Kobayashi, ``A Dsp-Based 3-D Sound Synthesis System for Moving Sound Images,'' In Proc. GAME-ON Conference, pp. 23--25, November 2003.
[220]  K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Modified Snake: Real-Time Face Object Extraction for Video Phone,'' In in Proc. IEEE International Conference on Image Processing(ICIP2003), Barcelona, Spain, vol. III, pp. 873--876, September 2003.
[221]  M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``Implementation of W-CDMA Channel Codec by Configurable Processors,'' In Proc. Sixth Baiona Workshop on Signal Processing in Communications, pp. 205--210, September 2003.
[222]  Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for TFT Liquid Crystal Displays,'' In in Proc. The European Solid-State Device Research Conference (ESSDERC2003) , Estoril, Portugul, pp. 453--456, September 2003.
[223]  H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Efficient Error Recovery Scheme for MPEG-4 Video Coding,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 2, pp. 1328--1331, July 2003.
[224]  Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for On-Chip Interconnects,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and ommunications (ITC-CSCC2003) , Kang-Woo Do, Korea, vol. 3, pp. 1638--1641, July 2003.
[225]  A. Kotani, Y. Asai, Y. Nakamura, S. Okada, N. Koyama, K. Yamane, Y.Okano, Y. Mitsuyama, and T. Onoye, ``Visibility Font Technology on High Resolution Color LCD "LCFONT.c",'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003), Kang-Woo Do, Korea, vol. 1, pp. 535--538, July 2003.
[226]  S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low Power Ogg Vorbis Decoder by Embedded Processor,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 1, pp. 565--568, July 2003.
[227]  T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Feature Extraction of Head-Related Transfer Function for 3D Sound Movement,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 1, pp. 685--688, July 2003.
[228]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources,'' In in IEEE 29th International Conference on Consumer Electronics (ICCE2003), digest of technical papers, Los Angeles, Carifornia, USA, pp. 256--257, June 2003.
[229]  T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, ``A Novel Signal Processing Scheme for Next Generation GNSS Receiver,'' In in Proc. the 8th ISU International Symposium, Strasbourg, France, May 2003.
[230]  M. Hatanaka, T. Masaki, M. Okada, and K. Murakami, ``Implementation of PSK Demodulator for Digital BS/{cs} Broadcasting System,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, vol. II, pp. 764--767, May 2003.
[231]  S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Interactive Interface of Realtime 3D Sound Movement for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, vol. II, pp. 520--523, May 2003.
[232]  Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Framework for JPEG2000 Encoding System Architecture,'' In Proc. International Symposium on Circuits and Systems, pp. 740--743, May 2003.
[233]  T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, ``A Novel Signal Processing Scheme for Next Generation GNSS Receiver and Its VLSI Implementation,'' In in Proc. International Signal Processing Conference , Dallas, no. 357, April 2003.
[234]  N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I.Shirakawa, ``Low Cost Approach to Acoustic Field Enhancement for Stereo Headphones,'' In in Proc. Euromedia 2003, Plymouth, United Kingdom, pp. 32--36, April 2003.
[235]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``A Parasitic Capacitance Modeling Method for Non-Planar Interconnects,'' In in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 294--299, April 2003.
[236]  T. Yuasa, A. Tomita, T. Izumi, T. Onoye, and Y. Nakamura, ``An Approach for Circuit Size Reduction by Variable Reordering for Pca-Chip2,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 217--221, April 2003.
[237]  T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa, ``Vlsi Architecture for Mpeg-4 Core Profile Codec Core,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 365--371, April 2003.
[238]  Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, ``Scalable Design Framework for JPEG2000 Encoder Architecture,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 372--376, April 2003.
[239]  T. Yuasa, Y. Soga, T. Izumi, T. Onoye, and Y. Nakamura, ``An Improved Communication Channel in Dynamic Reconfigurable Device for Multimedia Applications,'' In Proc. EUROMEDIA, pp. 152--157, April 2003.
[240]  K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Realtime Face Object Extraction Algorithm for Video Phone,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), Orchard Road, Singapore, vol. 1, pp. 35--38, December 2002.
[241]  Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, ``Implementation of Wireless MPEG2 Transmission System Using IEEE 802.11b PHY,'' In ibid, vol. 1, pp. 39--44, December 2002.
[242]  N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acousitic Field Enhancement for Stereo Headphones,'' In ibid, vol. 1, pp. 51--54, December 2002.
[243]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Multilevel Interconnects,'' In in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002, vol. 1, pp. 59--64, December 2002.
[244]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications,'' In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pp. 20--24, September 2002.
[245]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor,'' In in Proc. 17th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), Phuket, Thailand, pp. 94--97, July 2002.
[246]  S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Synthesis of 3D Sound Movement by Embedded DSP,'' In ibid, pp. 117--120, July 2002.
[247]  H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Digital Watermark Based Error Detection for MPEG-4 Bitstream Error,'' In ibid, pp. 152--155, July 2002.
[248]  T. Kaya, R. Miyamoto, T. Onoye, and I. Shirakawa, ``Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Processor,'' In ibid, pp. 216--219, July 2002.
[249]  H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Hybrid Error Concealment Algorithm for MPEG-4 Videodecoders,'' In ibid, pp. 611--614, July 2002.
[250]  K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, O. Tsumori, K. Hanada, T. Chiba, and I. Shirakawa, ``OCEAN: Object Communication Environment for Arbitrary Network,'' In in Proc. IEEE International Conference on Distributed Computing Systems Workshops, pp. 162--166, July 2002.
[251]  W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, ```Out-Of-Head' Acoustic Field Enhancement for Stereo Headphones by Embedded DSP,'' In in IEEE 28th International Conference on Consumer Electronics (ICCE2002), digest of technical papers, Cardiff, Wales, pp. 222--223, June 2002.
[252]  Y. Ohtani, N. Kawahara, T. Onoye, I. Shirakawa, and T. Chiba, ``MAC LSI Design for Wireless MPEG2 Transmission Over IEEE802.11b PHY,'' In ibid, pp. 242--243, June 2002.
[253]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``Burst Mode: a New Acceleration Mode for 128-Bit Block Ciphers,'' In in Proc. IEEE 24th Custom Integrated Circuits Conference (CICC2002), Orland, Florida, pp. 151--154, May 2002.
[254]  Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Digital Matched Filter and Prime Interleaver for W-CDMA,'' In Proc. IEEE International Symposium on Circuits and Systems (ISCAS2002), Phoenix, Arizona, vol. III, pp. 269--272, May 2002.
[255]  Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers,'' In ibid, vol. II, pp. 344--347, May 2002.
[256]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Power Estimation at Architecture Level for Embedded Systems,'' In ibid, vol. II, pp. 476--479, May 2002.
[257]  Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, and T. Chiba, ``Error Correction Block Based ARQ Protocol for Wireless Digital Video Transmission,'' In ibid, vol. I, pp. 605--608, May 2002.
[258]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``A Java Accelerator for High Performance Embedded Systems,'' In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.
[259]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Synthesis Algorithm for Monaural Sound Source,'' In in Proc. EUROMEDIA 2002, Modena, Italy, pp. 123--127, April 2002.
[260]  M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, ``High Performance Java Hardware Engine and Software Kernel for Embedded Systems,'' In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pp. 365--369, December 2001.
[261]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``An Architecture Level Power Estimation Method for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 78--85, October 2001.
[262]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``System Performance Evaluation of High-Speed Burst Mode for 128-Bit Block Ciphers,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 332--339, October 2001.
[263]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``High Performance Java Execution for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 346--350, October 2001.
[264]  M. Ise, Y. Uchida, T. Onoye, and I. Shirakawa, ``System-On-A-Chip Architecture for W-CDMA Baseband Modem LSI,'' In in Proc. The 4th International Conference on ASIC (ASICON 2001), Shanghai, pp. 364--369, October 2001.
[265]  M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa, ``Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 589--592, September 2001.
[266]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementaion of 3D Sound Localization Algorithm for Monaural Sound Source,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 1061--1064, September 2001.
[267]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Low Computational 3D Sound Localization Algorithm,'' In in Proc. 200l IEEE Workshop on Signal Processing Systems, Design and Implementation(SIPS 2001), Antwerp, Belgium, pp. 109--116, September 2001.
[268]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers,'' In in Proc. 14th Annual IEEE International ASIC/SoC Conference (ASIC/SoC2001), Washington, D.C., pp. W.1.1.1--W.1.1.5, September 2001.
[269]  H. Okada, H. S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Detection Based on Check Marker Embedding for MPEG-4 Video Coding,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 96--99, July 2001.
[270]  H. S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Concealment Algorithm by Motion Estimation Method for MPEG-4 Video Decoder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 104--107, July 2001.
[271]  T. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Low Power Architecture for H.263 Version2 Codec,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 620--623, July 2001.
[272]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Localization Algorithm,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 1140--1143, July 2001.
[273]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization for Monaural Sound Source,'' In in Proc. World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001), Orlando, Florida, USA, pp. 173--177, July 2001.
[274]  M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, ``Evaluation of Processor Code Efficiency for Embedded Systems,'' In in Proc. ACM 15th International Conference on Supercomputing, Sorrento, Italy, pp. 229--235, June 2001.
[275]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, vol. IV, pp. 734--737, May 2001.
[276]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A High Performance Burst Mode Approach for 128-Bit Block Ciphers,'' In in Proc. EUROMEDIA2001, Valencia, Spain, pp. 146--150, April 2001.
[277]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A Dynamically Reconfigurable Hardware-Based Cipher Chip,'' In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 11--12, January 2001.
[278]  R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``Realtime Wavelet Video Coder Based on Reduced Memory Accessing,'' In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 15--16, January 2001.
[279]  S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Portable MPEG-4 Audio Decoder,'' In in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA, pp. 80--84, September 2000.
[280]  Y. Dong, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder,'' In in Proc. International Conference on Image Processing (ICIP 2000), vol. III, pp. 126--129, September 2000.
[281]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A Shingle Chip Automotive Control LSI Using SOI BiCDMOS,'' In in Proc. of 2000 International Conference on Solid State Device and Materials, pp. 486-487, August 2000.
[282]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 253--256, July 2000.
[283]  W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 264--267, July 2000.
[284]  R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa, ``Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 811--814, July 2000.
[285]  T. Watanabe and N. Ishiura, ``Minimization of Spill Code Insertion by Register Constraint Analysis for Code Generation for Application Specific DSPs,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 953--956, July 2000.
[286]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Symposium on VLSI Circuits Digest of Technical Papers, Hawaii, USA, pp. 204--205, June 2000.
[287]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``Chameleon: a Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pp. 90--94, May 2000.
[288]  M. Hatanaka, T. Masaki, and K. Murakami, ``An Efficient Network Architecture for AAL Type2 and Its VLSI Implementation,'' In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pp. 123--125, May 2000.
[289]  R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a Realtime Wavelet Video Coder,'' In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pp. 543--546, May 2000.
[290]  N. Ishiura, T. Watanabe, and M. Yamaguchi, ``A Code Generation Method for Datapath Oriented Application Specific Processor Design,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pp. 71--78, April 2000.
[291]  M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, ``Thread Partitioning Method for Hardware Compiler Bach,'' In in Proc.\ Asia and South Pacific Design Automation Conference (ASP-DAC 2000), pp. 303--308, January 2000.
[292]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic,'' In in Proc. ASP-DAC2000, pp. 529--532, January 2000.
[293]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Video Coding Algorithm Based on Modified Discrete Wavelet Transform,'' In in Proc. NOLTA'99, vol. I, pp. 251--254, November 1999.
[294]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Architecture of Embedded Zerotree Wavelet Based Real-Time Video Coder,'' In in Proc. 12th IEEE ASIC/SOC Conference, pp. 137-141, October 1999.
[295]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Embedded Zerotree Wavelet Based Algorithm for Video Compression,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp.II-1343--1346, September 1999.
[296]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 872--875, September 1999.
[297]  M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa, ``High-Speed Implementation of JBIG Arithmetic Coder,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 1291--1294, September 1999.
[298]  N. Ishiura and M. Yamaguchi, ``Operation Binding for Retargetable Compilers Minimizing Clock Cycles,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 705--708, July 1999.
[299]  B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 561--564, July 1999.
[300]  M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa, ``Pipelined Implementation of JBIG Arithmetic Coder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 470--473, July 1999.
[301]  M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, ``Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, vol. IV, pp. 572--575, June 1999.
[302]  H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, ``Hybrid Media-Processor Core for Natural and Synthetic Video Decoding,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, vol. IV, pp. 275--278, June 1999.
[303]  G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``Low-Power Architecture of H.324 Codec Dedicated to Mobile Computing,'' In in Proc. EUROMEDIA'99 , Munich, Germany, pp. 145--149, April 1999.
[304]  K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, ``Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware,'' In in Proc. IEEE Internatinal Solid-State Circuits Conference, pp. 106--107, February 1999.
[305]  H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, ``Hybrid VLSI Architecture for Motion Compensation and Texture Mapping,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 383--386, November 1998.
[306]  J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, ``Structual Objeco-Oriented Video Segmentation and Representation Algorithm,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 78--82, November 1998.
[307]  H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura, ``Matrix-Vector Multiplier Module for Natural/Synthetic Hybrid Video Coding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 631--634, November 1998.
[308]  N. Ishiura, M. Yamaguchi, and T. Kambe, ``A Graph-Based Algorithm of Operation Binding for Compilers Targeting Heterogeneous Datapath,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 395--398, November 1998.
[309]  B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Implementation by a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 235--240, October 1998.
[310]  B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Delay and Power Simulation for a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. European Simulation Symposium, pp. 339--343, October 1998.
[311]  J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, ``Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding,'' In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pp. 141--151, September 1998.
[312]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System Constructed of SAW-Based Receiver/Transmitter and Its Applications to Medical Cares,'' In in Proc. IEEE Radio & Wireless Conf., pp. 47--50, August 1998.
[313]  Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Function Module for Texture Mapping and Motion Compensation,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 179--182, July 1998.
[314]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Implementation of DWT and EZW Cores for a Bitrate Scalable Video Coder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 221--224, July 1998.
[315]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System by Means of SAW-Based Transmitter/Receiver and Its Applications to Medical Cares,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 299--302, July 1998.
[316]  H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``Matrix-Vector Multiplier for Natural/Synthetic Hybrid Video Coding,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1269--1272, July 1998.
[317]  D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, ``VLSI Implementation of a Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1383--1386, July 1998.
[318]  N. Ishiura, M. Yamaguchi, and N. Nitta, ``Field Partitioning Algorithms for Compression of Instruction Codes of Application Specific VLIW Processors,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1387--1390, July 1998.
[319]  M. Yamaguchi, N. Ishiura, and T. Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal Datapath Architectures,'' In in Proc. International Symposium on Circuits and Systems, WPA4-4, June 1998.
[320]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data Systems Constructed of SAW-Divices and Its Applications to Medical Cares,'' In in Proc. Analog VLSI WS, pp. 39--44, June 1998.
[321]  G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``Implementation of H.324 Audiovisual Codec for Mobile Computing,'' In in Proc.\ IEEE Custom Integrated Circuits Conference, pp. 193--196, May 1998.
[322]  H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``A Low Power DSP Core Architecture for Low Bitrate Speech Codec,'' In in Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal Processing, pp. 3121--3124, May 1998.
[323]  M. Yamaguchi, N. Ishiura, and T. Kambe, ``Binding and Scheduling Algorithms for Highly Retargetable Compilation,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 93-98, February 1998.
[324]  T. Onoye, G. Fujita, H. Okuhata, M. H. Miki, and I. Shirakawa, ``Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 589-594, February 1998.
[325]  N. Ishiura and M. Yamaguchi, ``Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning,'' In in Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), pp. 105-109, December 1997.
[326]  T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Performance Evaluation of Shared VCI Cell for Multimedia ATM Network,'' In in Proc. International Seminar on Teletraffic and Network, pp. 482-485, November 1997.
[327]  H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi, ``A Unified Media-Processor Architecure for Video Coding and Computer Graphics,'' In in Proc. International Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional Imaging, pp. 253-256, September 1997.
[328]  M. H. Miki, G.Fujita, T. Onoye, and I. Sirakawa, ``Low-Power H.263 Video CoDec Dedicated to Mobile Computing,'' In in Proc. International Symposium on Low Power Electronics and Design, pp. 80-83, August 1997.
[329]  H. Uno, K. Kumatani, H. Okuhata, T. Chiba, and I. Shirakawa, ``Low Power Architecture for High Speed Infrared Wireless Communication System,'' In in Proc.International Symposium on Low Power Electronics and Design, pp. 255-258, August 1997.
[330]  Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``An Object Code Compression Approach to Embedded Processors,'' In in Proc. International Symposium on Low Power Electronics and Design, pp. 265-268, August 1997.
[331]  T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Fellow Cell Switching for Voice Communication on Multimedia ATM Network and Its VLSI Implementation,'' In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pp. 1219-1222, July 1997.
[332]  H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``Media-Processor Architecture Unified for Video Coding and 3D Graphics,'' In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pp. 1223-1226, July 1997.
[333]  G. Fujita, T. Onoye, and I. Sirakawa, ``A New Motion Estimation Core Dedicated to H.263 VideoCoding,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1161-1164, June 1997.
[334]  M.Yamaguchi, T. Nakaoka, A. Yamada, and T. Kambe, ``An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1584-1587, June 1997.
[335]  I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimun Cost Flow Algofithm for VLSI Layout Compaction,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1672-1675, June 1997.
[336]  T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Multimedia ATM Network Using Shared VCI Cell and VLSI Implementation of Rerouting Node,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 2793-2796, June 1997.
[337]  K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication,'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 229-232, May 1997.
[338]  H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Link Dedicated to Mobile Computing,'' In in Proc. IEEE International Performance, Computing, and Communications Conference, pp. 463-467, February 1997.
[339]  M. Yamaguchi, A. Yamada, T. Nakaoka, and T. Kambe, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pp. 503-508, January 1997.
[340]  S. Morikawa, K. Okada, S. Takeuchi, and I. Shirakawa, ``A High Performance FIR Filter Dedicated to Digital Video Transmission,'' In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pp. 77-82, January 1997.
[341]  H. Kondo, A. Sugiyama, and M. E. Cannon, ``Precise Carrier Phase GPS and Its Application to Real-Time Landslide Detection,'' In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pp. 906-911, November 1996.
[342]  G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura, ``Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pp. 949-954, November 1996.
[343]  H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Communication System Dedicated to Mobile Computing,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 334-337, November 1996.
[344]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 480-483, November 1996.
[345]  Y. Konno, K. Nakamura, T. Bitoh, K. Saga, and S. Yano, ``A Consistent Scan Design System for Large-Scale ASICs,'' In in Proc. Fifth Asian Test Symposium, pp. 82-87, November 1996.
[346]  Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low-Power Consumption Architecture for Embedded Processor,'' In in Proc. 2nd International Conference on ASIC, pp. 77-80, October 1996.
[347]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``Implementation of Very Low Bitrate Video Encoder Core,'' In in Proc. 2nd International Conference on ASIC, pp. 131-134, October 1996.
[348]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura, ``A Single Chip Motion Estimator Dedicated to MPEG2 MP@{hl},'' In in Proc. European Signal Processing Conference, pp. 1479-1482, September 1996.
[349]  G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa, ``Single Chip MPEG2 MP@{ml} Motion Estimator,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 286-289, July 1996.
[350]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Architecture for Very Low Bitrate Video Encoder Core,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 294-297, July 1996.
[351]  S. Nakamura, N. Ishiura, T. Yamamoto, and I. Shirakawa, ``High-Level Synthesis System for Behavioral Descriptions with Conditional Branches,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 935-938, July 1996.
[352]  Y. Shigehiro, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm and Its Application to VLSI Layout Compaction,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 951-954, July 1996.
[353]  H. Uno, K. Kumatani, H. Okuhata, T. Masaki, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Communication Link for Mobile Computing,'' In in Proc. Workshop on Multi-Dimensional Mobile Communications (MDMC '96), pp. 267-271, July 1996.
[354]  N. Shimizu, Y. Mizuta, H. Kondo, and H. Ono, ``A New GPS Real-Time Monitoring System for Deformation Measurements and Its Application,'' In in Proc. 8th FIG Int. Symp. Deformation Measurements, Hong Kong, S1.5, pp. 47-54, June 1996.
[355]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 351-354, May 1996.
[356]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``A VLSI Architecture of MPEG2 MP@{hl} Motion Estimator,'' In in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 664-667, May 1996.
[357]  K. Itoh, Y. Shigehiro, I. Shirakawa, and K. Matsumura, ``An Approach for Multi-Layer Gridless Routing,'' In in Proc. Printed Circuit World Convention VII, pp.P2-1-P2-7, May 1996.
[358]  N. Shimizu, K. Nakagawa, and H. Kondo, ``Displacement Monitoring by Using Global Positioning System,'' In in Proc. 4th Int. Symp. Field Measurements in Geomechanics, %Bergamo, Italy, pp. 555-562, April 1996.
[359]  M. Furuie, T. Onoye, S. Tsukiyama, and Isao Shirakawa, ``Two-Dimensional Array Layout for Low Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Conference on Electronics Packaging(2001 ICEP), Tokyo, April, 2001., pp. 417--421, .
国内会議(査読付き)
[1]  秋原 優樹, 廣瀬 哲也, 田中 勇気, 黒木 修隆, 沼 昌宏, 橋本 昌宜, ``小型センサデバイスに向けた無線給電システムの設計,'' 回路とシステムワークショップ, pp. 258--263, April 2015.
[2]  中島康祐, 伊藤雄一, Simon Voelker, Christian Thoresen, Kjell Ivar Øvergård, Jan Borchers, ``PUCs: 静電容量方式マルチタッチパネルにおけるユーザの接触を必要と しないウィジェット検出手法,'' インタラクション2014論文集, March 2014.
[3]  中島康祐, 伊藤雄一, 遠藤隆介, 岸野文郎, ``複合商業施設での複数人によるタイムスロット考慮型プランニングを実現するデジタルサイネージシステム,'' インタラクション2014論文集, March 2014.
[4]  中島康祐, 伊藤雄一, 林勇介, 池田和章, 藤田和之, 尾上孝雄, ``Emoballoon: ソーシャルタッチインタラクションのための柔らかな風船型インタフェース,'' インタラクション2013論文集, pp. 95-102, March 2013.
[5]  安藤正宏, 細井俊輝, 中島康祐, 伊藤雄一, 北村喜文, 尾上孝雄, ``ブロック型デバイスのための赤外線を用いた積み重ね形状認識におけるブロック間距離の影響に関する検討,'' 日本バーチャルリアリティ学会研究報告, vol. 18, no. CS-4, pp. 11-14, 2013.
[6]  小島康介, 橋本亮司, 藤田玄, ``H.264 向け量子化パラメータを考慮した動きベクトル検出手法の一検討,'' 第22回 回路とシステム軽井沢ワークショップ , pp. 142-147, April 2009.
研究会等発表論文
[1]  深町太一, 伊藤雄一, 尾上孝, ``光信号を用いたアクチュエータ群制御システムの検討と評価,'' 日本バーチャルリアリティ学会研究報告, vol. 21, no. CS-4, pp. 17-20, December 2016.
[2]  庄田 駿一, 劉 錦, 畠中 理英, 尾上 孝雄, ``ノード位置推定を用いた無線LANのスループット向上手法に関する研究,'' 第29回 回路とシステムワークショップ, pp. 81-83, May 2016.
[3]  續 毅海, 伊藤 雄一, 藤原 健, 高嶋 和毅, 尾上 孝雄, ``演奏者の重心移動を用いた演奏連携度の取得に関する検討,'' ヒューマンインタフェース学会研究会研究報告集, vol. 18, no. 5, pp. 15-18, 2016.
[4]  山下 真由, 伊藤 雄一, 高嶋 和毅, 尾上 孝雄, ``ペン把持力のセンシングによる筆記量推定手法,'' ヒューマンインタフェース学会研究会研究報告集, vol. 18, no. 5, pp. 3-8, 2016.
[5]  深町太一,伊藤雄一,尾上孝雄, ``汎用型光駆動アクチュエータのための制御ユニットの実装と評価,'' ヒューマンインタフェース学会研究会研究報告集, vol. 18, no. 7, pp. 31-34, 2016.
[6]  増田豊,橋本昌宜,尾上孝雄, ``電源ノイズ起因タイミング故障のデバッグにおける C 言語ベース故障検出手法の有効性評価,'' 情報処理学会DAシンポジウム, August 2015.
[7]  辻本 祐輝, 伊藤 雄一, 尾上 孝雄, ``結露を用いたディスプレイの結露生成機構に関する研究,'' 研究報告ヒューマンコンピュータインタラクション(HCI), vol. 2015-HCI-164, no. 5, pp. 001-005, July 2015.
[8]  E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, ``Hardware Architecture of Generic Soft Cascaded Linear Svm Classifier,'' , no. 75, 電子情報通信学会ディペンダブルコンピューティング研究会, June 2015.
[9]  檜原弘樹, 岩崎晃, 橋本昌宜, 越智裕之, 密山幸男, 小野寺秀俊, 神原弘之, 若林一敏, 杉林直彦, 竹中崇, 波田博光, 多田宗弘, ``センサの知能化に適したプロセッサアーキテクチャの考察,'' 電子情報通信学会ディペンダブルコンピューティング研究会, no. DC2015-8, pp. 43--48, April 2015.
[10]  S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, ``Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator,'' 電子情報通信学会 VLSI設計技術研究会, March 2015.
[11]  鵜川 翔平,信田 龍哉,橋本 昌宜,伊藤 雄一,尾上孝雄, ``クロスエントロピー法を用いたノード間距離情報に基づく3次元ノード位置推定,'' 情報処理学会ヒューマンコンピュータインタラクション研究会, January 2015.
[12]  土井龍太郎, 橋本昌宜, 尾上孝雄, ``時間的三重化によるソフトエラー耐性向上の解析的評価,'' 電子情報通信学会ディペンダブルコンピューティング研究会, November 2014.
[13]  岡田史也, 畠中理英, 尾上孝雄, ``ダイナミックスペクトルアクセス向けキャリアセンシング手法に関する一検討,'' 電子情報通信学会技術研究報告, vol. 114, no. 205, pp. 57-62, September 2014. (in Japanese)
[14]  飯塚翔一, 樋口裕磨, 橋本昌宜, 尾上孝雄, ``感度可変リングオシレータを用いた省面積デバイスパラメータばらつき推定手法,'' 情報処理学会DAシンポジウム, pp. 15--20, August 2014.
[15]  増田豊, 橋本昌宜, 尾上孝雄, ``電源ノイズ起因電気的故障を対象としたソフトウェアベース高速エラー検出手法の性能評価,'' 情報処理学会DAシンポジウム, pp. 203--208, August 2014.
[16]  宮崎陽平, 伊藤雄一, 藤原 健, 高嶋和毅, 尾上孝雄, ``着座揺動による会話者の行動の同期性検出に関する検討,'' HCS2014-53, August 2014.
[17]  冨田 幸佑, 畠中 理英, 尾上 孝雄, ``ダイナミックスペクトルアクセスを用いたOFDM送受信機のGPU実装に関する一検討,'' 電子情報通信学会技術研究報告, vol. 114, no. 122, pp. 81-86, July 2014.
[18]  飯塚翔一, 水野雅文, 黒田弾, 橋本昌宜, 尾上孝雄, ``プロセッサの適応的速度制御における故障発生時間見積り高速化に関する研究,'' LSIとシステムのワークショップ, May 2014.
[19]  河野仁, 鵜川翔平, 信田龍哉, 塚元瑞穂, 田中勇気, 中島康祐, 伊藤雄一, 廣瀬哲也, 橋本昌宜, ``リアルタイム3次元モデリングシステムiClayの実現に向けた1mm^3級センサノードの要素技術開発,'' LSIとシステムのワークショップ, May 2014.
[20]  郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, ``動的部分再構成による故障回避に適した初期配置配線の検討,'' 情報処理学会SLDM研究会, March 2014.
[21]  鵜川翔平, 信田龍哉, 伊藤雄一, 橋本昌宜, 尾上孝雄, ``ノード間距離情報に基づいた逐次的3次元ノード位置推定手法の検討,'' 信学技報 CAS研究会, March 2014.
[22]  橋本昌宜, ``オンチップばらつきモニタリングによる適応的性能補償 (Invited),'' 信学技報 集積回路研究会, January 2014.
[23]  菊地佑介, 津川翔, 岸野文郎, 中島康祐, 伊藤雄一, 大崎博之, ``ココロスコア: Twitter解析によるココロの状態推測,'' 電子情報通信学会 通信行動工学時限研専 第5回研究会予稿集, pp. 17-24, November 2013.
[24]  尾上孝雄, 橋本昌宜, 密山幸男, Dawood Alnajjar, 郡浦宏明, ``VLSIの信頼性を向上させる再構成可能アーキテクチャ (Invited),'' 信学技報リコンフィギャラブルシステム研究会, November 2013.
[25]  遠藤隆介, 伊藤雄一, 中島康祐, 岸野文郎, ``複合商業施設における複数人でのタイムスロット考慮型プランニングを実現するデジタルサイネージシステム,'' 情報処理学会研究報告集, vol. 2013-HCI-155, no. 9, pp. 1-8, October 2013.
[26]  安藤正宏, 細井俊輝, 中島康祐, 伊藤雄一, 北村喜文, 尾上孝雄, ``積み木型ブロックデ バイスのための赤外線による積み重ね認識手法に関する検討,'' ヒューマンインタフェース学会研究報告集, vol. 15, no. 7, pp. 125-128, September 2013.
[27]  飯塚翔一, 水野雅文, 黒田弾, 橋本昌宜, 尾上孝雄, ``適応的速度制御における連続時間マルコフ過程を用いた故障発生時間高速評価手法,'' 情報処理学会DAシンポジウム, August 2013.
[28]  福原優貴, 山田晃久, 尾上孝雄, ``画像の局所的特徴を利用したフレームメモリ容量削減のための画像圧縮手法,'' 信学技報, CAS2013-33, vol. 113, no. 118, pp. 183-188, July 2013.
[29]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討,'' 信学技報, RECONF2013-8, vol. 113, no. 52, pp. 41-46, May 2013.
[30]  藤本拓, 伊藤雄一, 中島康祐, 土方義徳, 尾上孝雄, ``ついでタスク推薦のためのコン ピュータ作業のクラスタリングに関する一検討,'' ARG Webインテリジェンスとイ ンタラクション研究会 第2回研究会予稿集, pp. 13-14, May 2013.
[31]  郡浦 宏明, Dawood Alnajjar, 密山 幸男, 越智 裕之, 今川 隆司, 野田 真一, 若林 一敏, 橋本 昌宜, 尾上 孝雄, ``C ベース設計に対応した信頼性可変粒度複合型再構成可能アーキテクチャ,'' LSIとシステムのワークショップ, May 2013.
[32]  原田 諒, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``放射線起因一過性パルスが信頼性に与える影響の実験的評価,'' LSI とシステムのワークショップ, May 2013.
[33]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法,'' 信学技報, VLD2012-154, vol. 112, no. 451, pp. 099-104, March 2013.
[34]  信田 龍哉, 橋本 昌宜, 尾上 孝雄, ``センサノード間静電容量結合に基づく距離推定に向けた電極形状の検討,'' 信学技報, CAS2012-119, vol. 112, no. 484, pp. 131-136, March 2013.
[35]  樋口裕磨, 橋本昌宜, 尾上孝雄, ``オンチップセンサを用いたばらつき自己補償手法の検討,'' 信学技報 VLSI設計技術研究会, March 2013.
[36]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的部分再構成による故障回避に関する一考察,'' 信学技報, RECONF2012-59 , vol. 112, no. 325, pp. 71-76, November 2012.
[37]  池田和章, 伊藤雄一, 中島康祐, 尾上孝雄, ``着座時の座面重心と重量を用いた個人識別に関する検討,'' ヒューマンインタフェース学会研究報告集, vol. 14, no. 8, pp. 11-16, September 2012.
[38]  藤田和之, 伊藤雄一, 高嶋和毅, 中島康祐, 林勇介, 岸野文郎, ``Ambient Party Room: パーティ場面における部屋型会話支援システムの構築,'' ヒューマンインタフェース学会研究報告集, vol. 14, no. 8, pp. 7-10, September 2012.
[39]  中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``立体形状の毛状マルチタッチ ディスプレイ,'' エンタテインメントコンピューティング2012論文集, pp. 195-198, September 2012.
[40]  竹内一貴, 尾上孝雄, ``多視点映像復号の組込み実装に関する一検討,'' 電子情報通信学会技術研究報告, vol. 112, no. 78, pp. 71-76, June 2012.
[41]  児島陽平, 伊藤雄一, 藤田和之, 中島康祐, 尾上孝雄, ``空間内の複数人員配置のための指示位置提示手法に関する検討,'' ヒューマンインタフェース学会研究報告集, vol. 14, no. 4, pp. 17-22, June 2012.
[42]  遠藤隆介, 伊藤雄一, 中島康祐, 藤田和之, 岸野文郎, ``マルチタッチディスプレイを用いたプランニングができるデジタルサイネージシステムの提案,'' ヒューマンインタフェース学会研究報告集, vol. 14, no. 4, pp. 37-42, June 2012.
[43]  保米本徹, 畠中理英, 尾上孝雄, ``ダイナミックスペクトルアクセスを用いた無線通信向けの伝搬路補償手法に関する一検討,'' 信学技報, CAS2011-126, vol. 111, no. 465, pp. 109-114, March 2012.
[44]  天木 健彦, 橋本 昌宜, 尾上 孝雄, ``ゆらぎ増幅回路を用いたオシレータベース物理乱数生成器,'' 信学技報, ICD2011-118, vol. 111, no. 352, pp. 087-092, December 2011.
[45]  池田和章, 林勇介, 中島康祐, 伊藤雄一, 尾上孝雄, ``風精―気圧センサと風船を用いたタッチインタラクション検出,'' エンタテインメントコンピューティング2011論文集, pp. 187-192, October 2011.
[46]  池田和章, 伊藤雄一, 中島康祐, 尾上孝雄, ``様々な椅子での重心・重量による姿勢識別率に関する検討,'' ヒューマンインタフェース学会研究報告集, vol. 13, no. 7, pp. 33-38, October 2011.
[47]  亀田 敏広, 郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``スキャンパスを用いたNBTI劣化抑制に関する研究,'' 情報処理学会DAシンポジウム, pp. 201-206, August 2011.
[48]  中前貴司, 山田晃久, 山口雅之, 尾上孝雄, ``フレームメモリ容量削減のための準可逆画像圧縮手法,'' 信学技報, CAS2011-29, vol. 111, no. 102, pp. 163-168, June 2011.
[49]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的再構成可能アーキテクチャによる故障回避機構の定量的評価,'' 信学技報, RECONF2011-6, vol. 111, no. 31, pp. 31-36, May 2011.
[50]  中島康祐, 伊藤雄一, 築谷喬之, 藤田和之, 高嶋和毅, 岸野文郎, ``FuSA2 Touch Display: 大画面毛状マルチタッチディスプレイ,'' インタラクション2011論文集, pp. 547-550, March 2011.
[51]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース物理乱数生成器の設計手法,'' 情報処理学会研究報告, SLDM2010-147, vol. 2010-SLDM-147, no. 19, pp. 1-6, November 2010.
[52]  岡田 雅司, 尾上 孝雄, 小林 亙, ``解析的二次音源モデルに基づく回折のレイトレーシングシミュレーション,'' 信学技報, EA2010-65, vol. 110 , no. 239 , pp. 043-048 , October 2010.
[53]  榎並 孝司, 木村 修太, 橋本 昌宜, 尾上 孝雄, ``自己性能補償に向けたカナリアFF挿入手法,'' 情報処理学会DAシンポジウム, pp. 227-232, September 2010.
[54]  三瓶 政一, 衣斐 信介, 宮本 伸一, 尾上 孝雄, 畠中 理英, ``アンビエント情報環境のための無線アクセスに関する一検討 ― 無線分散ネットワーク技術からのアプローチ ―,'' 信学技報, SR2009-112, vol. 109, no. 442, pp. 143-148, March 2010.
[55]  高井 康充, 橋本 昌宜, 尾上 孝雄, ``電源ノイズに注目した電源遮断法の実機評価,'' , no. 信学技報 vol.110, No344, 電子情報通信学会(IEICE), 2010.
[56]  黒田 弾, 更田 裕司, 橋本 昌宜, 尾上 孝雄, ``低エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価,'' 情報処理学会第141回システムLSI設計技術研究会, pp107-112, October 2009.
[57]  新開 健一, 橋本 昌宜, ``広範囲な製造・環境ばらつきに対応したゲート遅延モデル,'' 情報処理学会DAシンポジウム, pp. 73-78, August 2009.
[58]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``NBTI による劣化予測におけるトランジスタ動作確率算出法の評価,'' 情報処理学会DAシンポジウム, pp. 181-186, August 2009.
[59]  橋本 昌宜, 榎並 孝司, 新開 健一, 二宮 進有, 阿部 慎也, ``電源ノイズや製造ばらつきによるクロックジッタ・スキューを考慮した統計的タイミング解析,'' 情報処理学会DAシンポジウム, pp. 79-84, August 2009.
[60]  松下裕丈, 河村侑輝, 尾上孝雄, 大原一人, 芥子育雄, ``携帯機器における動画像ストリーム高速簡略復号の一手法,'' IEICE Technical Report SIS2009-4 (2009-6), pp. 19-24, June 2009.
[61]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``マルコフモデルによるオシレータサンプリング方式真性乱数生成器の乱数品質解析,'' 第22回回路とシステム軽井沢ワークショップ, pp. 474-479, April 2009.
[62]  達可敏充, 橋本亮司, 渡邊賢治, 畠中理英, 尾上孝雄, ``ダイナミックスペクトルアクセスを用いたコグニティブ無線ネットワークにおけるノード位置推定手法の一検討,'' 信学技報, IN2008-220, vol. 108, no. 458, pp. 523-528, March 2009.
[63]  濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``レイアウトを考慮した基板バイアスクラスタリング手法,'' 信学技報, VLD2008-159 , vol. 108, no. 478, pp. 195-200, March 2009.
[64]  榎並 孝司, 橋本 昌宜, 佐藤 高史, ``電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法,'' 信学技報, VLD2008-161, vol. 108, no. 478, pp. 207-212, March 2009.
[65]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証,'' 信学技報, VLD2008-159, vol. 108, no. 478, pp. 201-206, March 2009.
[66]  橋本亮司, 筒井 弘, 尾上孝雄, 猪飼知宏, ``DCT領域 Distributed Video Coding における尤度推定手法,'' 信学技報, IE2008-209, vol. 108, no. 425, pp. 31-36, February 2009.
[67]  小島康介, 橋本亮司, 藤田玄, ``H.264向けRDOに基づいた動きベクトル検出手法の一検討,'' 電子情報通信学会技術研究報告, SIP2008-99, vol. 104, no. 213, pp. 53-58, September 2008.
[68]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析,'' 情報処理学会DAシンポジウム, pp. 217-222, August 2008.
[69]  渡邊賢治, 達可敏充, 畠中理英, 尾上孝雄, ``屋内位置推定システムのための間取り推定に関する一検討,'' 信学技報, USN2008-33, vol. 108, no. 138, pp. 129-134, July 2008.
[70]  廣本 正之, 筒井 弘, 越智 裕之, 小佐野 智之, 石川 憲洋, 中村 行宏, ``メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法の検討,'' マルチメディア,分散,協調とモバイル(DICOMO2008)シンポジウム, pp. 1167-1176, July 2008.
[71]  河村 侑輝, 真鍋 安武, 尾上 孝雄, 大原 一人, 岡田 浩行, 芥子 育雄, ``動画像並列復号のマルチコアプロセッサへの実装,'' 信学技報, SIS2008-23, vol. 108, no. 86, pp. 51-56, June 2008.
[72]  岡田 雅司, 岩永 信之, 松村 友哉, 尾上 孝雄, 小林 亙, ``ファジィクラスタリングに基づく多音源立体音像定位手法,'' 信学技報, SIS2008-1, vol. 108, no. 85, pp. 001-006, June 2008.
[73]  濱本 浩一, 更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``基板バイアス印加レイアウト方式の面積効率と速度制御性の評価,'' 信学技報, CAS2008-14, VLD2008-27, SIP2008-48(2008-6), pp. 75-79, June 2008.
[74]  服部 幸市, 筒井 弘, 越智 裕之, 中村 行宏, ``バス帯域を考慮した HD Photo における Photo Core Transform のアーキテクチャ,'' 信学技報, SIS2008-21, vol. 108, no. 85, pp. 39-44, June 2008.
[75]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``バス配線による誘導性クロストークノイズによる遅延変動の実測とノイズ重ねあわせ効果の検証,'' , 信学技報, VLD2007-153, March 2008.
[76]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``スタンダードセルで構成された電源ノイズ波形測定回路の提案,'' 信学技報, CPM2007-131, ICD2007-142, pp. 17-22, January 2008.
[77]  加藤裕視, 山田晃久, 尾上孝雄, ``フレームメモリの削減を目的とした画像圧縮手法,'' 電子情報通信学会 CAS信学技報, vol. 107, no. 476, pp. 31-36, January 2008.
[78]  二宮 進有, 橋本 昌宜, ``SSTAにおける空間的相関を持つ製造ばらつきのグリッドベースモデル化法の検討,'' 信学技報, VLD2007-91, DC2007-46, vol. 107, no. 336, pp. 13-17, November 2007.
[79]  橋本亮司, 加藤公也, 才辻誠, 田中照人, 上津寛和, 藤田玄, 尾上孝雄, ``1080HD向けマルチシンボルH.264エントロピー復号器,'' 第21回ディジタル信号処理シンポジウム, November 2007.
[80]  加藤 公也, 橋本 亮司, 藤田 玄, 尾上 孝雄, ``H.264 High ProfileにおけるマルチシンボルCABAC復号器のアーキテクチャ検討,'' 信学技報, SIP2007-121, ICD2007-110, IE2007-80, pp. 65-70, October 2007.
[81]  橋本 昌宜, ``製造・環境ばらつきを考慮したタイミング検証技術,'' 信学技報, VLD2007-65, pp. 21-24, October 2007.
[82]  阿部 慎也, 橋本 昌宜, 尾上 孝雄, ``製造ばらつきを考慮したメッシュ型クロック分配網のスキュー評価,'' 情報処理学会DAシンポジウム, pp. 133-138, August 2007.
[83]  筒井 弘, 藤田 憲正, 尾上 孝雄, 中村 行宏, ``JPEG2000 マルチシンボル算術復号器,'' 信学技報, SIS2007-3, vol. 107, no. 93, pp. 13--18, June 2007.
[84]  新開 健一, 橋本 昌宜, 尾上 孝雄, ``短距離ブロック内配線の自己発熱,'' 第 20 回 回路とシステム軽井沢ワークショップ, pp. 7-12, April 2007.
[85]  榎並 孝司, 二宮 進有, 橋本 昌宜, ``電源ノイズの空間的相関を考慮した統計的タイミング解析,'' 第20回 回路とシステム軽井沢ワークショップ, pp. 667-672, April 2007.
[86]  橋本 昌宜, ``製造・環境ばらつきと動的性能補償を考慮したタイミング検証に向けて,'' 第20回 回路とシステム(軽井沢)ワークショップ, pp. 661-666, April 2007.
[87]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測,'' 信学技報, CPM2006-131, ICD2006-173, pp. 13--18, January 2007.
[88]  小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄, ``電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法,'' 信学技報, CPM2006-132, ICD2006-174, pp. 19--23, January 2007.
[89]  松村 友哉, 吉田 明弘, 岩永 信之, 小林 亙, 尾上 孝雄, ``頭部伝達関数による立体音像移動の移動感向上に関する一手法,'' 日本音響学会聴覚研究会資料, vol. 36, no.9, H--2006--135, December 2006.
[90]  吉田 明弘, 松村 友哉, 岩永 信之, 小林 亙, 尾上 孝雄, ``頭部近傍における立体音像定位の向上に関する一手法,'' 日本音響学会聴覚研究会資料, H-2006-134, December 2006.
[91]  橋本 亮司, 藤田 玄, 尾上 孝雄, ``H.264符号化における演算量動的割当ての一手法,'' 第21回ディジタル信号処理シンポジウム, D8-1, November 2006.
[92]  種村 嘉高, 小谷 章夫, 山崎 聖一, 密山 幸男, 尾上 孝雄, ``視覚特性を考慮した文字の黒み推定に関する一検討,'' 電子情報通信学会技術研究報告, vol. 106, no. 374, pp. 69--74, November 2006.
[93]  野里 良裕, 高橋 和之, 奥畑 宏之, 尾上 孝雄, ``リアルタイム動画像Retinex階調補正における照明光推定器のアーキテクチャ,'' 第21回ディジタル信号処理シンポジウム, D8-3, November 2006.
[94]  Jangsombatsiri Siriporn, 橋本 昌宜, 尾上 孝雄, ``シャントコンダクタンスを挿入したオンチップ伝送線路特性評価,'' 第十回シリコンアナログRF研究会, November 2006.
[95]  榎並 孝司, 橋本 昌宜, 尾上 孝雄, ``主成分分析による電源電圧変動の統計的モデル化手法,'' 情報処理学会DAシンポジウム, pp. 205--210, July 2006.
[96]  高橋和之, 野里良裕, 奥畑宏之, 尾上孝雄, ``変分法によるRetinex階調補正の演算量削減検討,'' 信学技報 SIS2006-3, pp. 13--18, June 2006.
[97]  藤田 玄, 大窪 啓太, 上甲 憲市, 才辻 誠, 尾上 孝雄, ``低動作周波数によるH.264 CABACのリアルタイム処理実現手法,'' 信学技報 SIS2006-34, pp. 19--23, June 2006.
[98]  新開 健一, 橋本 昌宜, 黒川 敦, 尾上孝雄, ``電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル,'' 第19回 回路とシステム軽井沢ワークショップ, pp. 559-564, April 2006.
[99]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``LSI配線における容量性, 誘導性クロストークノイズの定量的将来予測,'' 第19回回路とシステム軽井沢ワークショップ, pp. 5--10, April 2006.
[100]  伊勢正尚, 小笠原泰弘, 渡邊賢治, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``IEEE 802.15.4を用いたホームネットワーク向け無線ネットワークプロトコル,'' 信学技報, CAS2005-99, pp. 19--24, March 2006.
[101]  渡邊賢治, 伊勢正尚, 藤田玄, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``無線ホームネットワークにおける消費電力および即時性の改善手法,'' 信学技報, CAS2005-100, pp. 25--30, March 2006.
[102]  伊地知孝仁, 橋本昌宜, 高橋真吾, 築山修治, 白川功, ``画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術,'' 信学技報, VLD2005-131, pp. 55--60, March 2006.
[103]  今福哲也, 岩永信之, 松村友哉, 小林亙, 尾上孝雄, ``多音源に対する立体音像移動手法,'' 信学技報, SP2005-192, pp. 47-52, March 2006.
[104]  藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4向け高精度動き検出コアのVLSI化設計,'' 電子情報通信学会, vol. J88-A, no. 11, pp. 1282--1291, November 2005.
[105]  小谷 章夫, 種村 嘉高, 朝井 宣美, 中村 安久, 大塚 正章, 密山 幸男, 尾上 孝雄, ``文字重心位置評価手法とその可読性評価への応用,'' 信学技報, SIS2005-23, pp. 1--6, September 2005.
[106]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``誘導性・容量性クロストークノイズによる遅延変動の測定と評価,'' 信学技報, SDM2005-135, ICD2005-74, pp. 43--48, August 2005.
[107]  吉田 明弘, 松村 友哉, 岩永 信之, 小林 亙, 尾上 孝雄, ``近距離音像の定位を実現するための頭部伝達関数の特徴解析,'' 信学技報, EA2005-39, pp. 29--34, August 2005.
[108]  野里 良裕, 奥畑 宏之, 尾上 孝雄, 白川 功, ``適応的階調補正のハードウェア実現における Retinex 理論の比較評価,'' 信学技報, SIS2005-16, pp. 19--24, June 2005.
[109]  藤田玄, 今仲隆晃, フィン ヴァン ニャット, 尾上孝雄, 白川功, ``色空間のブロック分割に基づく携帯端末向けリアルタイム人オブジェクト抽出手法,'' 第18回 回路とシステム軽井沢ワークショップ, pp. 431--436, April 2005.
[110]  ワットカナッド・ウィラポーン, 木村基, 藤田玄, 尾上孝雄, 白川功, ``動画像マルチデコーダ用動き補償機構のVLSIアーキテクチャ,'' 信学技報, SIS2004-62, pp. 37--43, March 2005.
[111]  郭朝暉, 西川裕規, 大巻 ロベルト 裕治, 尾上 孝雄, 白川 功, ``Motion JPEG2000 における誤り訂正符号の割当て手法,'' 信学技報, CAS2004-67, pp. 1--6, January 2005.
[112]  盧 承烈, 小笠原 泰弘, 伊勢 正尚, 畠中 理英, 尾上 孝雄, 庭本 浩明, 芥子 育雄, 白川 功, ``ユニバーサルプラグアンドプレイ技術を用いたホームネットワーク一構成方式,'' 信学技報, CAS2004-68, pp. 7--12, January 2005.
[113]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線間容量抽出手法,'' 信学技報, VLD2004-64, pp. 19--24, December 2004.
[114]  小谷 章夫, 朝井 宣美, 中村 安久, 大塚 正章, 密山 幸男, 尾上 孝雄, ``文字輪郭を用いた重心位置評価手法に関する一検討,'' 情報処理学会研究報告, 2004-HI-111, pp. 63--70, November 2004.
[115]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``組込みシステム向け IEEE802.11i 暗号処理回路の実装,'' 信学技報, ICD2004-129, pp. 49--54, October 2004.
[116]  今井 林太郎, 密山 幸男, 尾上 孝雄, 白川 功, ``メディア処理向けリコンフィギュラブルアーキテクチャに関する一検討,'' 電子情報通信学会 第4回リコンフィギャラブルシステム研究会, pp. 33--40, September 2004.
[117]  木村基, 密山幸男, 尾上孝雄, 白川功, ``組込みシステム向け IEEE 802.11i 暗号処理器のアーキテクチャ,'' 第17回回路とシステム軽井沢ワークショップ, pp. 217--222, April 2004.
[118]  中川陽介, 岩永信之, 小林亙, 古谷一彦, 尾上孝雄, 白川功, ``周波数特性除去に基づくスピーカによるバイノーラル再生,'' 聴覚研究会, pp. 17--22, January 2004.
[119]  内田 好弘, 谷 貞宏, 築山 修治, 白川 功, ``領域分割による配線間容量モデル化手法について,'' 信学技報, NLP2003-21, pp. 7--12, June 2003.
[120]  岩永信之, 阪本憲成, 小林亙, 尾上孝雄, 白川功, ``組込みシステム向けヘッドホンステレオ頭外音場拡大手法とその実装,'' 第17回 ディジタル信号処理シンポジウム, B2-4, November 2002.
[121]  河原 伸幸, 大谷 昌弘, 尾上 孝雄, 白川 功, ``IEEE802.11b を用いた映像伝送システムの設計,'' 第17回 ディジタル信号処理シンポジウム, B6-1, September 2002.
[122]  小坂篤史, 山口悟史, 奥畑宏之, 尾上孝雄, 白川功, ``組み込みCPUと専用回路によるOgg Vorbis音楽デコーダのVLSI化設計,'' 信学技報, SDM2002-159, ICD2002-70, pp. 37--42, August 2002.
[123]  谷 貞宏, 内田 好弘, 築山 修治, 白川 功, ``配線間容量モデル化とその評価について,'' 信学技報 DSP2002-83, pp. 7--12, June 2002.
[124]  岡田 勉, 内田 翼, 尾上 孝雄, 白川 功, ``次世代衛星航法システム受信機のための擬似雑音符号生成器の構成,'' 信学技報 DSP2002-69, pp. 19--24, June 2002.
[125]  宋 学燮, Alten-Erdene Shiitev, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4ビデオ符号化におけるエラー隠蔽アルゴリズムの提案,'' 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pp. 95--100, April 2002.
[126]  中川 克哉, 川北 将, 佐藤 康二, 花田 恵太郎, 千葉 徹, 白川 功, ``異機種間適応型オブジェクト共有環境,'' 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pp. 161--166, April 2002.
[127]  水野 洋, 小林 弘幸, 尾上 孝雄, 白川 功, ``組込みシステムアーキテクチャレベルにおける消費電力見積り手法,'' 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pp. 435--440, April 2002.
[128]  中川 貴史, 濱中 慎介, 肖 云和, 藤田 玄, 白川 功, ``MPEG-4 コア・プロファイル・コーデックの VLSI アーキテクチャ,'' 信学技報, VLD2001-136, pp. 31--38, January 2002.
[129]  木村 基, 三木 裕介, 尾上 孝雄, 白川 功, ``組込みシステム向け Java 実行環境の構築,'' 信学技報, VLD2001-137, pp. 39--44, January 2002.
[130]  大谷 昌弘, 河原 伸幸, 戸丸 知信, 丸山 一人, 尾上 孝雄, 白川 功, ``映像伝送システムのための誤り訂正ブロック単位 ARQ 手法,'' 第16回 ディジタル信号処理シンポジウム, C8-6, pp. 711--717, November 2001.
[131]  大谷 昌弘, 河原 伸幸, 中岡 弘幸, 戸丸 知信, 丸山 一人, 尾上 孝雄, 白川 功, ``データフレーム選択再送手法に基づいた映像伝送システムの設計,'' 信学技報, VLD2001-93, pp. 25--30, November 2001.
[132]  中川克哉, 佐藤康二, 津森靖, 花田恵太郎, 白川功, ``任意ネットワーク対応オブジェクトコミュニケーション環境 (OCEAN),'' 情報処理学会 第 104 回 マルチメディアと分散処理(石切)研究会, pp. 19--24, September 2001.
[133]  宋 学燮, Altan-Erdene Shiitev, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4 ビデオ伝送に対するエラー隠蔽アルゴリズムおよびアーキテクチャ,'' 信学技報, CAS2001-10, pp. 71--77, June 2001.
[134]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``ブロック暗号の高速化暗号モードとその VLSI 化設計,'' 信学技報, CAS2001-41, pp. 89--94, June 2001.
[135]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``3 次元音像定位リアルタイムアルゴリズムの DSP 実装とその評価,'' 信学技報, CAS2001-50, pp. 147--154, June 2001.
[136]  藤田 玄, 樽家 昌也, 本谷 謙治, 奥畑 宏之, 白川 功, ``顔オブジェクトのリアルタイム抽出アルゴリズム,'' 信学技報 DSP2001-31, pp. 87--92, June 2001.
[137]  三木 裕介, 坂本 守, 武内 良典, 吉田 豊彦, 白川 功, ``組込みシステム向きプロセッサのコード効率に関する評価,'' 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 113--118, April 2001.
[138]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A New Approach for 128-Bit Block Ciphers,'' In 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 231--236, April 2001.
[139]  宋 天, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``H.263 Version2 コーデックコアの VLSI 化設計,'' 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 561--566, April 2001.
[140]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``モノラル音の実時間 3 次元音像定位アルゴリズムの 1 チップ DSP 実装,'' 信学会 第 15 回ディジタル信号処理シンポジウム C6-2, pp. 599--604, November 2000.
[141]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP 用リターゲッタブルコンパイラによるデータパス指向協調設計手法,'' 信学技報, VLD2000-89, pp. 119--124, November 2000.
[142]  宋 学燮, 宋 天, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``動き検出を利用した MPEG-4 ビデオにおけるエラー隠蔽アルゴリズムの提案,'' 信学技報, DSP2000-107, pp. 37--43, October 2000.
[143]  宋 天, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``H.263 拡張 INTRA 符号化モードのコーデックとその VLSI とその VLSI アーキテクチャ,'' 信学技報, DSP2000-108, pp. 45--50, October 2000.
[144]  中川 克哉, 川北 将, 佐藤 康二, 水口 充, 白川 功, ``異機種間オブジェクトコミュニケーション環境,'' マルチメディア, 分散, 協調とモバイル(DICOMO 2002) シンポジウム, pp. 197--200, July 2000.
[145]  小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``3 次元音像定位リアルタイムアルゴリズムとその低消費電力 DSP 実装,'' 信学技報, CAS2000-13, pp. 97--102, June 2000.
[146]  黒田 涼, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4 向け省面積 SA-DCT の VLSI 化設計,'' 信学技報, CAS2000-14, pp. 103--108, June 2000.
[147]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いたハードウェア向き暗号方式,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 367--372, April 2000.
[148]  山田 昇平, 三木 Morgan 裕介, 藤田 玄, 尾上 孝雄, 白川 功, ``低ビットレート動画像符号化 VLSI 実装向きビットレート制御,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 385--390, April 2000.
[149]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``特定用途向け DSP のデータパス指向協調設計におけるコード生成手法,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 539--544, April 2000.
[150]  丹羽 章雅, 橋本 晋弥, 奥畑 宏之, 尾上 孝雄, 白川 功, ``携帯用 MPEG-4 オーディオデコーダの VLSI 化設計,'' 第14回ディジタル信号処理シンポジウム, pp. 629--634, November 1999.
[151]  Zaldy ANDALES, 密山 幸男, 浅利 康二, 尾上 孝雄, 白川 功, ``リコンフィグラブルハードウェアを用いた暗号システム,'' 信学技報, CAS99-63, NLP99-87, pp. 7--14, September 1999.
[152]  古家 眞, 宋 宝玉, 吉田 幸弘, 尾上 孝雄, 白川 功, ``4相NMOSダイナミックロジック用アレイセル,'' 信学技報, CAS99-62, pp. 1--6, September 1999.
[153]  三木 Morgan 裕介, 山田 昇平, 藤田 玄, 尾上 孝雄, 白川 功, ``携帯端末用 H.263 動画像コーデックの VLSI 設計,'' DA シンポジウム 99, pp. 183--188, July 1999.
[154]  古家 眞, 松村 謙次, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘, ``医療用監視システムのための通信制御用LSI,'' 信学技報, CAS99, pp. 15--19, June 1999.
[155]  大卷 ロベルト 裕治, 藤田 玄, 尾上 孝雄, 白川 功, ``離散ウエーブレット変換に基づく動画像符号化器のアーキテクチャ,'' 信学技報, CAS99-33, pp. 21--28, June 1999.
[156]  高橋 瑞樹, 石浦 菜岐佐, 山田 晃久, 神戸 尚志, ``ハードウェアコンパイラBachにおけるスレッド分割手法,'' 信学会 第12回回路とシステム(軽井沢)ワークショップ, pp. 103--108, April 1999.
[157]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``非直交なデータパスに対するリターゲッタブルコンパイラのスケジューリング手法,'' 信学会 第12回回路とシステム軽井沢ワークショップ, pp. 109--114, April 1999.
[158]  畠中 理英, 正城 敏博, 尾上 孝雄, 村上 孝三, ``AAL Type2 スイッチの制御方式とアーキテクチャの設計,'' 信学会 第12回回路とシステム軽井沢ワークショップ, pp. 427--432, April 1999.
[159]  服部 靖史, 石浦 菜岐佐, 山口 雅之, ``DSP向けリターゲッタブルコンパイラの演算器/転送経路のバインディング手法,'' 信学技報, VLD98-125, vol. 98, no. 447, pp. 55-61, December 1998.
[160]  藤嶋 秀幸, 竹本 裕介, 米田友和, 尾上 孝雄, 白川 功, ``動画像復号化と3次元グラフィックスで共用可能なメディアプロセッサ向き演算モジュールの設計,'' 信学技報, VLD98-41, pp. 31--38, September 1998.
[161]  滝大輔, M.H. Miki, 藤田玄, 尾上孝雄, 白川功, 藤原融, 嵩忠雄, ``再帰的最尤復号アルゴリズムを用いた誤り訂正復号器の VLSI 設計,'' 信学技報, VLD98-52, pp. 57--62, September 1998.
[162]  密山 幸男, 浅利 康二, 尾上 孝雄, 白川 功, 馬場 孝明, 大槻 達男, ``強誘電体メモリを用いた Reconfigurable Logic とその性能評価,'' 信学技報, ICD98-120, pp. 53--58, August 1998.
[163]  竹本 裕介, 米田 友和, 藤嶋 秀幸, 尾上 孝雄, 白川 功, ``テクスチャマッピングおよび動き補償用共有回路の VLSI 化設計,'' 信学技報, VLD98-33, pp. 19--26, July 1998.
[164]  三木裕介, 藤田玄, 奥畑宏之, 尾上孝雄, 白川功, ``携帯端末用 H.324 符号化/復号化方式とその VLSI 化設計,'' 信学会 第11回回路とシステム軽井沢ワークショップ, pp. 439--444, April 1998.
[165]  竹本裕介, 藤嶋秀幸, 尾上孝雄, 白川功, ``動画像復号化と3次元コンピュータグラフィクス向き行列ベクトル乗算器のアーキテクチャ,'' 信学会 第11回回路とシステム軽井沢ワークショップ, pp. 451--456, April 1998.
[166]  山口雅之, 石浦菜岐佐, 神戸尚志, ``非直交なデータパスに対するリターゲッタブルコンパイラのバインディング手法,'' 信学会 第11回回路とシステム軽井沢ワークショップ, pp. 481--486, April 1998.
[167]  奥畑宏之, 三木裕介 Morgan, 尾上孝雄, 白川功, ``低ビットレート音声符号化用DSPのVLSI化設計,'' 第12回ディジタル信号処理シンポジウム, pp. 651-655, November 1997.
[168]  藤嶋秀幸, 竹本裕介, 尾上孝雄, 白川功, ``動画像と3次元CGを扱うメディアプロセッサのアーキテクチャに関す る研究,'' 第2回映像メディア処理シンポジウム, pp. 23-24, October 1997.
[169]  宮野鼻晃士, 藤田玄, 柳田和弘, 尾上孝雄, 白川 功, ``携帯環境向き低ビットレート動画像通信システムのVLSI 化設計,'' 電子情報通信学会技術研究報告, DSP97-107, vol. 97, no. 315, pp. 17-24, October 1997.
[170]  藤田 玄, 三木 裕介 Morgan, 尾上 孝雄, 白川 功, ``携帯端末用 H.263 符号化/復号化 VLSI の設計,'' 第12回画像符号化シンポジウム, pp. 51-52, October 1997.
[171]  山口雅之, 石浦菜岐佐, 神戸尚志, ``組込み式システム向けリターゲッタブルコンパイラの方式,'' 電子情報通信学会技術研究報告, VLD97-90, FTS97-53, pp. 85-92, October 1997.
[172]  山本哲三朗, 石浦菜岐佐, 山口雅之, 服部靖史, ``組込みシステム向け高位合成システム,'' 電子情報通信学会技術研究報告, VLD97-91, FTS97-54, pp. 93-99, October 1997.
[173]  澤卓, 長尾明, 白川功, 神戸尚志, 千原國宏, ``方形パッキング手法による MMIC 向き配置配線手法,'' 電子情報通信学会技術研究報告, VLD97-97, FTS97-60, pp. 141-146, October 1997.
[174]  荒井正, 水谷宣明, 会津隆士, 近藤仁志, ``GPSを用いた連続変位量観測による地すべり移動特性について\ ---長野県倉並地すべりの例---,'' 第36回地すべり学会研究発表講演集, pp. 365-368, August 1997.
[175]  澤卓, 長尾明, 神戸尚志, 白川功, 千原國宏, ``方形パッキング法の一算法,'' 電子情報通信学会技術研究報告, DSP97-53, pp. 159-166, June 1997.
[176]  矢野政顕, 石浦菜岐佐, ``スキャンパス構成を利用した内蔵メモリの試験,'' 電子情報通信学会第10回回路とシステム軽井沢ワークショップ, pp. 95-100, April 1997.
[177]  長尾明, 澤卓, 磯部雅哉, 神戸尚志, 白川功, ``マイクロ波集積回路向きレイアウト設計に対する自動化手法,'' 電子情報通信学会第10回回路とシステム軽井沢ワークショップ, pp. 433-438, April 1997.
[178]  正城敏博, 中谷泰寛, 尾上孝雄, 村上孝三, ``音声通信を考慮したマルチメディアATM通信方式とVLSI化,'' 電子情報通信学会技術研究報告, IN97-10, pp. 39-46, April 1997.
[179]  清水則一, 近藤仁志, 宮下耕一, 小野浩, ``GPS地盤変位モニタリングシステムによる残壁の長期観測実験,'' 第28回岩盤力学に関するシンポジウム講演論文集, pp. 388-392, January 1997.
[180]  山口雅之, 中岡敏博, 神戸尚志, ``データパス構成と並列制約にもとづくアーキテクチャ評価システム,'' 電子情報通信学会技術研究報告, VLD96-74, CPSY96-86, pp. 71-78, December 1996.
[181]  中谷泰寛, 正城敏博, 尾上孝雄, 村上孝三, ``VCI 共有セルを用いたマルチメディア ATM 通信手法と VLSI 設計,'' 電子情報通信学会技術研究報告, DSP96-90, vol. 96, no. 301, pp. 39-46, October 1996.
[182]  宮野鼻晃士, 藤田玄, 尾上孝雄, 白川功, ``低ビットレート画像符号化アルゴリズムとその VLSI 化設計,'' 電子情報通信学会技術研究報告, DSP96-89, vol. 96, no. 301, pp. 33-38, October 1996.
[183]  森川俊, 岡田圭介, 竹内澄高, 白川功, ``高性能定係数FIRフィルタのVLSI化設計,'' 情報処理学会DAシンポジウム'96, pp. 41-46, August 1996.
[184]  佐藤洋, 森本康夫, 正城敏博, 尾上孝雄, 白川功, ``1チップ MPEG2 デコーダの設計と動き補償器の VLSI 実装,'' 情報処理学会DAシンポジウム'96, pp. 47-52, August 1996.
[185]  近藤仁志, ``GPSの地すべり計測への応用,'' 第40回システム制御学会研究発表講演会 (チュートリアルセッション), pp. 15-20, May 1996.
[186]  清水則一, 小野浩, 近藤仁志, 水田義明, ``長大残壁の安全監視へのGPS変位計測システムの応用に関する現場実験,'' 資源と素材, vol. 112, pp. 283-288, May 1996.
[187]  森川俊, 岡田圭介, 竹内澄高, 白川功, ``ディジタル映像伝送向け高性 能FIRフィルタのVLSI化設計,'' 電子情報通信学会第9回回路とシステム軽 井沢ワークショップ, pp. 359-364, April 1996.
[188]  S. Yano, K. Akagi, and N. Ishiura, ``A New Scan Path Approach to Memory Array Testing,'' In 電子情報通信学会第9回回路とシステム軽 井沢ワークショップ, pp. 55-60, April 1996.
著書
[1]  M. Hashimoto and R. Nair, ``Power Integrity for Nanoscale Integrated Systems,'' McGraw-Hill Professional, February 2014.
[2]  伊藤雄一, 中島康祐, “ふさふさ”感触マルチタッチディスプレイの開発, 株式会社エヌ・ティー・エス, 2013.
[3]  伊藤雄一, 中島康祐, 「ふさふさ」した触り心地を実現する光ファイバによる毛状マ ルチタッチディスプレイ, 株式会社技術情報協会, 2013.
解説
[1]  佐藤高史, 橋本昌宜, ``経時劣化概説,'' 信頼性学会誌, vol. 35, no. 8, pp. 457--458, December 2013.
[2]  橋本昌宜, ``超低電力サブスレッショルド回路設計技術 ,'' IEICE Fundamentals Review, pp. 30--37, July 2013.
[3]  清川 清, 畠中 理英, 細田 一史, 岡田 雅司, 繁田 浩功, 石原 靖哲, 大下 福仁, 角川 裕次, 栗原 聡, 森山 甲一, ``オーエンス・ルイス:アンビエント環境制御を用いた知的オフィスチェアの提案,'' システム制御情報学会誌, vol. 56, no. 1, pp. 14-20, January 2012.
[4]  伊藤雄一, 中島康祐, ``〜「ふさふさ」した触り心地〜 光ファイバによる毛状マルチタッチディスプレイ,'' MATERIAL STAGE, vol. 11, no. 8, pp. 13-16, November 2011.
[5]  橋本昌宜, ``遅延ばらつきを考慮したVLSIタイミング検証,'' エレクトロニクス実装学会誌, vol. 11, no. 3, pp. 182--185, May 2008.
大会等発表論文
[1]  佐藤雅紘, 飯塚翔一, 粟野皓光, 橋本昌宜, 尾上孝雄, ``NBTIによる閾値電圧変化の確率的モデル化に関する一考察,'' 2015年電子情報通信学会総合大会講演論文集, March 2015.
[2]  河野仁, 橋本昌宜, 近藤利彦, 森村浩季, ``超小型コイルを用いた近距離無線通信における周辺コイルの影響評価,'' 2015年電子情報通信学会総合大会講演論文集, March 2015.
[3]  益田涼平, 橋本昌宜, 尾上孝雄, ``サーモパイル型赤外線センサを用いた人感センサの性能評価,'' 2015年電子情報通信学会総合大会講演論文集, March 2015.
[4]  宮崎陽平, 伊藤雄一, 藤原 健, 高嶋和毅, 尾上孝雄, ``SenseChairによる会話者間の同調傾向検出,'' 情報処理学会インタラクション2015論文集, March 2015.
[5]  安藤正宏, 細井俊輝, 伊藤雄一, 高嶋和毅, 北村喜文, ``StackBlock: 積み重ね形状認識可能なブロック型UI,'' 情報処理学会インタラクション論文集, 2015.
[6]  宮崎陽平, 伊藤雄一, 藤原 健, 高嶋和毅, 尾上孝雄, ``SenseChairを用いた眠気検出に関する検討,'' 情報処理学会インタラクション2014論文集, March 2014.
[7]  安藤正宏, 細井俊輝, 中島康祐, 高嶋和毅, 伊藤雄一, 足立智昭, 尾上孝雄, 北村喜文, ``StackBlock: 積み重ね形状構築を可能とするブロック型デバイス,'' 情報処理学会インタラクション論文集, pp. 135-142, 2014.
[8]  宮崎陽平, 安藤正宏, 藤田悠矢, 羽鹿諒, Ondreicka Merrielle, 伊藤雄一, ``ケツログラフィティ: 結露を用いたインタラクティブディスプレイ,'' EC2013, October 2013.
[9]  中川雄太, 岸野文郎, 中島康祐, 伊藤雄一, ``半球状の毛状マルチタッチディスプレイにおけるタッチインタラクション認識,'' 日本バーチャルリアリティ学会第18回大会論文集, pp. 659-660, September 2013.
[10]  井藤佑哉, 岸野文郎, 中島康祐, 伊藤雄一, ``毛状ディスプレイの特定領域内での触感変化に関する検討,'' 日本バーチャルリアリティ学会第18回大会論文集, pp. 390-391, September 2013.
[11]  作田賢志朗, 安部晋一郎, 渡辺幸信, 原田諒, 橋本昌宜, 更田裕司, 上村大樹, ``宇宙線中性子起因マルチセルアップセットのスケーリング則調査,'' 応用物理学会秋期学術講演会, September 2013.
[12]  根本祐輔, 中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``吹きかけインタラク ションのための入力検出法の検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 213, March 2013. (A-16-7)
[13]  富田健太郎, 中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``毛状ディスプレイの触感変化に関する検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 214, March 2013. (A-16-8)
[14]  内田將太郎, 岸野文郎, 池田和章, 中島康祐, 伊藤雄一, ``SenseChairを用いた眠気検出に関する検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 215, March 2013. (A-16-9)
[15]  岡田 雅司, 畠中 理英, 尾上 孝雄, ``秘匿化機能の分散化に基づくセキュアなアンビエント無線通信システムの実装,'' 第14回 DSPS教育会議 予稿集, pp. 71-72, September 2012.
[16]  藤本拓, 伊藤雄一, 石原のぞみ, 中島康祐, 尾上孝雄, ``タブレットデバイスと目の位置関係を考慮した電子書籍表示手法に関する検討,'' ヒューマンインタフェースシンポ ジウム2012論文集, pp. 701-704, September 2012.
[17]  中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``半球状の毛状マルチタッチディスプレイ,'' 日本バーチャルリアリティ学会第17回大会論文集, pp. 300-303, September 2012.
[18]  藤井佑一, 岸野文郎, 藤田和之, 中島康祐, 伊藤雄一, 菊池日出男, ``U-brella: 降り注ぐ情報を可振化するポータブル傘型インタフェース,'' 日本バーチャルリアリティ学会第17回大会論文集, pp. 652-655, September 2012.
[19]  上野 美保, 橋本 昌宜, 尾上 孝雄, ``電気的タイミング故障のデバッグ向けオンチップリアルタイム電源電圧センサ,'' 電子情報通信学会2009ソサイエティ大会2012, vol. A-3-6, p. 53, September 2012.
[20]  岡田 雅司, 尾上 孝雄, 小林 亙, ``GPU レイトレーサと多音源音像定位手法を用いた対話的な三次元音場生成システム,'' 電子情報通信学会総合大会, A-20-7, March 2012.
[21]  竹中拓也, 岸野文郎, 藤田和之, 中島康祐, 伊藤雄一, ``二者間の着座状態と会話の活性度の関係に関する検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 220, March 2012. (A-14-2)
[22]  中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``立体毛状マルチタッチディスプレイの一検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 261, March 2012. (A-16-12)
[23]  川幡尚亮, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``インテリアへの適用を考慮した毛状ディスプレイの耐荷重に関する検討,'' 電子情報通信学会総合大会講演論文集 (基礎・境界), p. 262, March 2012. (A-16-13)
[24]  金田征悟, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``毛状ディスプレイのための吹きかけインタラクションの検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 263, March 2012. (A-16-14)
[25]  藤枝智子, 岸野文郎, 中島康祐, 池田和章, 伊藤雄一, ``着座姿勢の歪みを是正するシステムに向けたセンシングの基礎検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 266, March 2012. (A-16-17)
[26]  菊地佑介, 岸野文郎, 石原のぞみ, 中島康祐, 伊藤雄一, ``形容詞クエリを用いた連想意味関係の名詞抽出に関する検討,'' 電子情報通信学会総合大会講演論文集(基礎・境界), p. 267, March 2012. (A-16-18)
[27]  清川 清, 畠中 理英, 細田 一史, 岡田 雅司, 繁田 浩功, 石原 靖哲, 大下 福仁, 角川 裕次, 栗原 聡, 森山 甲一, ``オーエンス・ルイス −アンビエント環境制御を用いた知的オフィスチェアの開発−,'' ヒューマンインターフェースシンポジウム, September 2011.
[28]  中瀬 絢哉, 栗原 聡, 森山 甲一, 石原 靖哲, 大下 福仁, 角川 裕次, 清川 清, 畠中 理英, 細田 一史., ``カフェ・ド・ナイーダ:アンビエント環境における最適インタラクション推定機構の提案,'' ヒューマンインターフェースシンポジウム, September 2011.
[29]  林 勇介, 伊藤 雄一, 中島 康祐, 藤田 和之, 高嶋 和毅, 大坊 郁夫, 尾上 孝雄, ``カップ型デバイス Cup-le を用いた会話実験支援手法,'' ヒューマンインターフェースシンポジウム2011論文集, September 2011.
[30]  藤田和之, 高嶋和毅, 伊藤雄一, 大崎博之, 小野直亮, 香川景一郎, 津川翔, 中島康祐, ``Ambient Suite: 部屋型情報空間を用いた対人コミュニケーション支援,'' ヒューマンインタフェースシンポジウム2011論文集, pp. 395-400, September 2011.
[31]  橋本 亮司, 達可 敏充, 畠中 理英, 尾上 孝雄, 畑本 浩伸, 衣斐 信介, 宮本 伸一, 三瓶 政一, ``ダイナミックスペクトルアクセスを用いたOFDM無線送受信機のFPGA実装,'' 電子情報通信学会総合大会, AS-2-2, March 2010.
[32]  中村 秀幸, 筒井 弘, 橋本 亮司, 尾上 孝雄, ``特徴点追跡を用いた動き補償フレーム補間手法,'' 電子情報通信学会2009ソサイエティ大会, A-20-14, p. 204, September 2009.
[33]  橋本 亮司, 加藤 公也, 藤田 玄, 尾上 孝雄, ``H.264 CABAC復号器の高速化に関する一検討,'' 電子情報通信学会2008ソサイエティ大会,A-20-9, September 2008.
[34]  橋本亮司, 藤田玄, 尾上孝雄, ``1080HD向けH.264 CAVLC復号器の高速化に関する一検討,'' 電子情報通信学会2007ソサイエティ大会,A-20-16, September 2007.
[35]  山崎 聖一, 密山 幸男, 尾上 孝雄, ``文字重心位置を利用した文字ストローク自動補正手法の検討,'' 電子情報通信学会 2007ソサイエティ大会, A-20-13, September 2007.
[36]  筒井 弘, ``古いフィルム映像を模擬した劣化動画像の符号化手法,'' 電子情報通信学会2007ソサイエティ大会, AK-2-3, September 2007. (2007年電子情報通信学会ソサイエティ大会基礎・境界ソサイエティ特別企画「若手研究者のための映像圧縮コンテスト」最優秀賞受賞)
[37]  榎並 孝司, 橋本 昌宜, ``統計的電源ノイズモデル化に適した適応的領域分割法,'' 電子情報通信学会ソサイエティ大会, pp. A-3-10, September 2007.
[38]  河村 侑輝, 橋本 亮司, 尾上孝雄, ``H.264符号化における1/4画素精度動き検出の性能評価,'' 電子情報通信学会2007ソサイエティ大会,A-4-28, September 2007.
[39]  橋本亮司, 松村友哉, 野里良裕, 渡邊賢治, 尾上孝雄, ``複眼光学系による物体注視システムのハードウェア実現,'' 第9回 DSPS教育者会議 予稿集, pp. 87-88, August 2007.
[40]  二宮 進有, 橋本 昌宜, ``空間的相関を考慮したSSTAにおける領域の分割数と精度,'' 電子情報通信学会総合大会, A-3-1 , March 2007.
[41]  濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``低電圧回路向け基板電位制御レイアウト方式の面積効率評価,'' 電子情報通信学会総合大会, A-3-6, March 2007.
[42]  阿部 慎也, 橋本 昌宜, 尾上 孝雄, ``メッシュ型クロック分配網のスキュー評価,'' 電子情報通信学会総合大会, A-3-5, March 2007.
[43]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``加算器を用いたsubthreshold 回路の設計指針の検討,'' 電子情報通信学会総合大会, A-3-17, March 2007.
[44]  Siriporn Jangsombatsiri, 橋本昌宜, 土谷亮, Haikun Zhu, Chung-Kuan Cheng, ``シャントコンダクタンスを挿入したオンチップ伝送線路のアイパターン評価,'' 電子情報通信学会総合大会, A-3-9, March 2007.
[45]  新開 健一, 橋本 昌宜, 尾上 孝雄, ``短距離ブロック内配線の自己発熱問題の将来予測,'' 電子情報通信学会ソサイエティ大会, pp. A-3-14, September 2006.
[46]  加藤 公也, 橋本 亮司, 藤田 玄, 尾上 孝雄, ``時間的・空間的隣接ヘッダ情報に基づくH.264イントラ予測モード判定手法,'' 電子情報通信学会ソサイエティ大会, September 2006.
[47]  Mohd Nadzrul Mohd Nor, Tomoya Matsumura, and Takao Onoye, ``Improvement of Direction of Arrival Estimation of Speech Using Two-Channel Microphone Array with Angle Position Realignment,'' In IEICE Society Conference, A-4-32, September 2006.
[48]  榎並 孝司, 橋本 昌宜, 尾上 孝雄, ``電源ノイズ解析のための回路動作部表現法の評価,'' 電子情報通信学会総合大会, A-3-16, March 2006.
[49]  橋本 亮司, 藤田 玄, 尾上 孝雄, ``動画像の動き量に基づくH.264符号化パラメータ設定手法,'' 電子情報通信学会総合大会, D-11-42, March 2006.
[50]  高橋 真吾, 築山 修治, 橋本 昌宜, 白川 功, ``液晶ディスプレイ用サンプリング回路の設計手法について,'' 2005 年電子情報通信学会ソサイエティ大会講演論文集, A-3-4, 2005.
[51]  重信優也, 尾上孝雄, 白川功, ``MPEG-2符号化情報に基づくMPEG-2/MPEG-4トランスコーディングの一手法,'' 電子情報通信学会 第19回信号処理シンポジウム, D4-4, November 2004.
[52]  今仲隆晃, 藤田玄, 尾上孝雄, 白川功, ``携帯端末向けリアルタイム人オブジェクト抽出,'' 第19回信号処理シンポジウム, D1-3, November 2004.
[53]  小坂 篤史, 奥畑 宏之, 尾上 孝雄, 白川 功, ``組込み向けOgg Vorbis デコーダシステムの設計,'' 電子情報通信学会 第19回信号処理シンポジウム, C7-1, November 2004.
[54]  渡邊 賢治, 西田 秀治, 藤田 玄, 尾上 孝雄, 白川 功, ``エージェント技術に基づくホームネットワーク制御システム,'' 電子情報通信学会ソサイエティ大会, A-1-30, September 2004.
[55]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶に適した配線間容量抽出の検討,'' 電子情報通信学会ソサイエティ大会, A-1-16, September 2004.
[56]  奥畑 宏之, 小坂 篤史, 松村 友哉, 尾上 孝雄, 白川 功, ``Retinex 輝度補正のリアルタイム動画像向け演算量削減手法,'' 電子情報通信学会ソサイエティ大会, A-4-22, September 2004.
[57]  川北将, 藤田玄, 尾上孝雄, 白川功, ``リアルタイム JPEG - MPEG-4 トランス コーダの実装,'' 信学会 総合大会, A-4-7, March 2004.
[58]  Y. D. Handoko, 宋天, 藤田玄, 尾上孝雄, 白川功, ``低演算量 H.264 向け動き検出アルゴリズム TS-ME の VLSI 化設計,'' 信学会 総合大会, A-4-10, March 2004.
[59]  中川 克哉, 川北 将, 尾上孝雄, 千葉 徹, 白川 功, ``適合的情報空間連係の利便性の考察,'' 情報処理学会 第2回 情報科学技術フォーラム(FIT2003), vol. 4, pp. 267--268, September 2003.
[60]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``無線 LAN セキュリティ拡張規格向け暗号処理器のアーキテクチャ,'' 電子情報通信学会ソサイエティ大会, A-4-4, September 2003.
[61]  今仲 隆晃, 本谷 謙治, 藤田 玄, 尾上 孝雄, 白川 功, ``顔領域に基づく携帯端末向けリアルタイム髪オブジェクト抽出,'' 電子情報通信学会ソサイエティ大会, A-4-26, September 2003.
[62]  前田真一, 山口悟史, 小坂篤史, 奥畑宏之, 山田晃久, 尾上孝雄, 白川功, ``Bach C言語によるOgg VorbisデコーダのVLSI化設計,'' 信学会 総合大会, A-3-8, March 2003.
[63]  岩永信之, 阪本憲成, 小林亙, 尾上孝雄, 白川功, ``ヘッドホンステレオ頭外音場拡大手法の組込み実装,'' 信学会 ソサイエティ大会, A-4-20, September 2002.
[64]  内田 翼, 岡田 勉, 尾上 孝雄, 白川 功, ``次世代衛星航法システム対応汎用擬似雑音符号生成器の実装,'' 信学会 ソサイエティ大会, A-5-15, September 2002.
[65]  伊勢 正尚, 内田 好弘, 尾上 孝雄, 白川 功, ``W-CDMA 用階層化ディジタルマッチトフィルタ,'' 信学会 ソサイエティ大会, A-1-7, September 2001.
[66]  内田 好弘, 伊勢 正尚, 尾上 孝雄, 白川 功, ``W-CDMA ターボ符号処理向け VLSI アーキテクチャ,'' 信学会 ソサイエティ大会, A-1-8, September 2001.
[67]  三木 裕介, 坂本 守, 河原 伸幸, 武内 良典, 吉田 豊彦, 白川 功, ``組込みシステム用実行ファイルの効率的圧縮および実行方法の提案,'' 信学会 ソサイエティ大会, A-3-15, September 2001.
[68]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``モノラル音 3 次元音像定位処理システムのハードウェア実装,'' 信学会 ソサイエティ大会, A-4-40, September 2001.
[69]  中川 貴史, 濱中 慎介, 藤田 玄, 白川 功, ``MPEG-4 動き補償用パディング処理の VLSI 化設計,'' 信学会 ソサイエティ大会, A-4-41, September 2001.
[70]  小林 弘幸, 水野 洋, 尾上 孝雄, 白川 功, ``組込みシステムにおける消費電力見積りの一手法,'' 信学会 ソサイエティ大会, SA-1-1, September 2001.
[71]  Altan-Erdene Shiitev, 岡田 浩行, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``電子透かしを用いた MPEG-4 ビデオ伝送におけるエラー検出方式の検討,'' 信学会 ソサイエティ大会, D-11-38, September 2001.
[72]  岡田 浩行, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4 ビデオ符号化における電子透かしを利用したエラー検出方式,'' 2001 画像電子学会年次大会一般セッション, pp. 19--20, June 2001.
[73]  Gulistan Raja, 宋 天, 藤田 玄, 尾上 孝雄, 白川 功, ``H.263 向きデブロッキングフィルタおよび拡張 Intra 符号化処理の VLSI 化設計,'' 信学会 総合大会, A-3-7, March 2001.
[74]  山口 悟史, 小坂 篤史, 奥畑 宏之, 白川 功, ``組み込み CPU 向け Ogg Vorbis デコーダの VLSI 実装,'' 信学会 総合大会, A-3-8, March 2001.
[75]  小俣 真也, 阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``3 次元音像移動アルゴリズムの DSP 実装,'' 信学会 総合大会, A-4-55, March 2001.
[76]  密山 幸男, 岩永 信之, 尾上 孝雄, 白川 功, ``Bluetooth スキャッタネットの構築手法と経路制御,'' 信学会 総合大会, A-4-68, March 2001.
[77]  本谷 謙治, 藤田 玄, 白川 功, ``改良 SNAKES による顔オブジェクト高速抽出手法,'' 信学会 総合大会, D-12-15, March 2001.
[78]  小俣 真也, 小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``汎用 DSP 実装用 3 次元音像定位リアルタイムアルゴリズム,'' 映像情報メディア学会 冬季大会, 1-11, December 2000.
[79]  三木 裕介, 尾上 孝雄, 白川 功, ``組込みプロセッサ向け Java アクセラレータの VLSI 化設計,'' 信学会 ソサイエティ大会, A-3-12, October 2000.
[80]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP のコード生成におけるスピルコードの最小化,'' 信学会 ソサイエティ大会, A-3-20, October 2000.
[81]  小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``3 次元音像定位のための実時間アルゴリズム,'' 信学会 ソサイエティ大会, A-4-23, October 2000.
[82]  濱中 慎介, 黒田 涼, 藤田 玄, 白川 功, ``MPEG-4 リバーシブル可変長復号器の VLSI 化設計,'' 信学会 ソサイエティ大会, A-4-41, October 2000.
[83]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いた暗号方式,'' 信学会 ソサイエティ大会, A-4-42, October 2000.
[84]  橋本 晋弥, 丹羽 章雅, 奥畑 宏之, 尾上 孝雄, 白川 功, ``MPEG-4 オーディオデコーダにおけるノイズレス復号器およびスペクトル 予測器の VLSI 化設計,'' 信学会 ソサイエティ大会, A-3-4, September 1999.
[85]  大下勝, 尾上孝雄, 白川功, ``JBIG 算術符号化部の高速化設計,'' 信学会 総合大会, A-4-32, March 1999.
[86]  山田昇平, 三木 Morgan 裕助, 藤田玄, 尾上 孝雄, 白川 功, ``H.263 符号化におけるビットレート制御に関する研究,'' 信学会 ソサイエティ大会, B-8-31, October 1998.
[87]  竹本 裕介, 藤嶋 秀幸, 尾上 孝雄, 白川 功, ``画像符号化と3次元CGで共用可能な行列・ベクトル乗算器,'' 信学会 総合大会, C-12-19, May 1998.
[88]  石浦菜岐佐, 山口雅之, ``特定用途向けVLIW型プロセッサの命令コード圧縮手法,'' 電子情報通信学会ソサイエィ大会, A-3-10, August 1997.
[89]  藤田玄, 尾上孝雄, 白川功, ``H.263用 DCT/IDCT演算コアのVLSI化設計,'' 電子情報通信学会ソサイエティ大会, C-12-28, August 1997.
[90]  宮野鼻晃士, 柳田和弘, 尾上孝雄, 白川功, ``低ビットレート動画像通信システムのVLSI化設計,'' SCI第41回システム制御情報学会研究発表講演会, pp. 247-248, May 1997.
[91]  森川俊, 岡田圭介, 竹内澄高, 白川功, ``映像伝送用高性能ディジタルフィルタの VLSI 化設計,'' 電子情報通信学会総合大会, A-4-29, March 1997.
[92]  藤田玄, Itthichai Arungsrisangchai, 尾上孝雄, 白川功, ``H.263 向け動き検出器の VLSI 化設計,'' 電子情報通信学会総合大会, SC-11-2, March 1997.
[93]  正城敏博, 中谷泰寛, 尾上孝雄, 村上孝三, ``VCI 共有セルを用いた ATM 音声通信手法,'' 電子情報通信学会ソサイエティ大会, SB-10-2, September 1996.
[94]  吉田幸宏, 宋宝玉, 奥畑宏之, 尾上孝雄, 白川功, ``組み込み用プロセッサの低消費電力化に対する一手法,'' 電子情報 通信学会ソサイアティ大会, SA-1-2, September 1996.
[95]  中岡敏博, 山口雅之, 山田晃久, 神戸尚志, ``評価システムを用いたプログ ラム方式専用プロセッサの設計支援,'' 情報処理学会 第53回全国大会, 2B-1, pp. 21-22, September 1996.

This site is maintained by Onoye Lab.

PMAN 2.5.5 - Paper MANagement system / (C) 2002-2008, Osamu Mizuno / All rights reserved.