Paper - Onoye Lab.

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Academic Journal: [1] T. Minamikawa, D. Nagai, T. Kaneko, I. Taniguchi, M. Ando, R. Akama, and K. Takenaka, ``Analytical Imaging of Colour Pigments Used in Japanese Woodblock Prints Using Raman Microspectroscopy,'' Journal of Raman Spectroscopy, vol. 48, no. 12, pp. 1887-1895, December 2017.; [2] Takemi Tsuzuki, Yuischi Itoh, Masahiro Ando, Toshiki Hosoi, Kazuki Takashima, Takao Onoye, Yoshifumi Kitamura, ``Stackblock: a Block-Shaped Interface for 3d Model Reconstruction of Stacked Blocks,'' 情報処理学会論文誌, vol. 57, no. 12, pp. 2565-2576, December 2016.; [3] Yuki Tsujimoto, Yuichi Itoh, Takao Onoye, ``Ketsuro-Graffiti: an Interactive Display with Water Condensation,'' 日本バーチャルリアリティ学会論文誌, vol. 21, no. 3, pp. 513-520, September 2016.; [4] C. Siriteanu, A. Takemura, C. Koutschan, S. Kuriki, D. Richards, and H. Shin, ``Exact Zf Analysis and Computer-Algebra-Aided Evaluation in Rank-1 Los Rician Fading,'' IEEE Transactions on Wireless Communications, accepted, April 2016.; [5] Constantin Siriteanu, Satoshi Kuriki, Donald Richards, and Akimichi Takemura, ``Chi-Square Mixture Representations for the Distribution of the Scalar Schur Complement in a Noncentral Wishart Matrix,'' Statistics and Probability Letters, accepted, February 2016.; [6] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, ``Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E98-A, no. 12, pp. 2607--2613, December 2015.; [7] Kosuke TOMITA, Masahide HATANAKA, and Takao ONOYE, ``Implementation of Viterbi Decoder Toward GPU-Based SDR Receiver,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E98-A, no. 11, pp. 2246-2253, November 2015.; [8] T.T. Oo, T. Onoye, and K. Shin, ``Partial Encryption Method That Enhances MP3 Security,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E98-A, no. 8, pp. 1760-1768, August 2015.; [9] D. Fukuda, K. Watanabe, Y. Kanazawa, and M. Hashimoto, ``Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E98-A, no. 7, pp. 1467--1474, July 2015.; [10] T. Shinada, M. Hashimoto, and T. Onoye, ``Proximity Distance Estimation Based on Electric Field Communication between 1mm³ Sensor Nodes,'' Analog Integrated Circuits and Signal Processing, May 2015.; [11] C.Siriteanu, A.Takemura, S.Kuriki, and H.Shin, ``Mimo Zero-Forcing Performance Evaluation Using the Holonomic Gradient Method,'' IEEE Transactions on Wireless Communications, vol. 14, no. 4, p. 2322 - 2335, April 2015.; [12] C.Siriteanu, A.Takemura, S.Kuriki, D.Richards, and H.Shin, ``Schur Complement Based Analysis of Mimo Zero-Forcing for Rician Fading,'' IEEE Transactions on Wireless Communications, vol. 14, no. 4, pp. 1757-1771, April 2015.; [13] S. Hirokawa, R. Harada, M. Hashimoto, and T. Onoye, ``Characterizing Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4-V Srams,'' IEEE Transactions on Nuclear Science, April 2015.; [14] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518--2529, December 2014.; [15] T. Amaki, M. Hashimoto, and T. Onoye, ``A Process and Temperature Tolerant Oscillator-Based True Random Number Generator,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2393--2399, December 2014.; [16] D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, and M. Hashimoto, ``Edge-Over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2373--2382, December 2014.; [17] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Exploring Well-Configurations for Minimizing Single Event Latchup,'' IEEE Transactions on Nuclear Science, vol. 61, no. 6, pp. 3282--3289, December 2014.; [18] H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1468--1482, July 2014.; [19] H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Nbti Mitigation Method by Inputting Random Scan-In Vectors in Standby Time,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1483--1491, July 2014.; [20] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1461--1467, July 2014.; [21] 遠藤隆介, 伊藤雄一, 中島康祐, 岸野文郎, ``マルチタッチディスプレイを用いた複数人によるプランニングができるデジタルサイネージシステムの提案,'' 情報処理学会論文誌, vol. 55, no. 4, April 2014.; [22] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10t Subthreshold Sram,'' IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, p. 463 -- 470, March 2014.; [23] C.Siriteanu, S.D. Blostein, A.Takemura, H.Shin, S.Yousefi, and S.Kuriki, ``Exact Mimo Zero-Forcing Detection Analysis for Transmit-Correlated Rician Fading,'' IEEE Transactions on Wireless Communications, vol. 13, no. 3, pp. 1514-1527, March 2014.; [24] Sho Tsugawa, Hiroyuki Ohsaki, Yuichi Itoh, Naonori Ono, Keiichiro Kagawa, and Kazuki Takashima, ``Dynamic Social Network Analysis with Heterogeneous Sensors in Ambient Environment,'' Social Networking, vol. 3, no. 1, pp. 9-18, January 2014.; [25] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, vol. 21, no. 12, p. 2165 -- 2178, December 2013.; [26] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4362--4367, December 2013.; [27] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft-Error in Sram at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4232--4237, December 2013.; [28] M. Okada, M. Hatanaka, K. Kagawa, and S. Miyamoto, ``Realization of Secure Ambient Wireless Network System Based on Spatially Distributed Ciphering Function,'' IEICE Trans. on Fundamentals of Electronics, vol. E96-A, no. 11, November 2013.; [29] 中島康祐, 伊藤雄一, 林勇介, 池田和章, 藤田和之, 尾上孝雄, ``Emoballoon: ソーシャルタッチインタラクションのための柔らかな風船型インタフェース,'' 日本バーチャルリアリティ学会論文誌, vol. 18, no. 3, pp. 255-265, September 2013.; [30] K. Shinkai, M. Hashimoto, and T. Onoye, ``A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations,'' Integration, the VLSI Journal, vol. 46, no. 4, pp. 345--358, September 2013.; [31] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement,'' IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 2630--2634, August 2013.; [32] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,'' IEICE Trans. on Information and Systems , vol. E96-D, no. 8, pp. 1624--1631, August 2013.; [33] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling,'' IEEE Transactions on Information Forensics and Security, vol. 8, no. 8, pp. 1331--1342, August 2013.; [34] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Supply Noise Suppression by Triple-Well Structure,'' IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp. 781--785, April 2013.; [35] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices,'' IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.; [36] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, ``A 0.8-V 110-Na Cmos Current Reference Circuit Using Subthreshold Operation,'' IEICE Electronics Express (ELEX), vol. 10, no. 4, March 2013.; [37] T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 3, pp. 684--696, March 2013.; [38] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 2, pp. 459--468, February 2013.; [39] 藤田和之, 高嶋和毅, 伊藤雄一, 大崎博之, 小野直亮, 香川景一郎, 津川翔, 中島康祐, 林勇介, 岸野文郎, ``Ambient Suiteを用いたパーティ場面における部屋型会話支援システムの実装と評価,'' 電子情報通信学会論文誌, vol. J96-D, no. 1, pp. 120-132, January 2013.; [40] Yusuke Hayashi, Yuichi Itoh, Kazuki Takashima, Kazuyuki Fujita, Kosuke Nakajima, and Takao Onoye, ``Cup-Le: Cup-Shaped Tool for Subtly Collecting Information during Conversational Experiment,'' The International Journal of Advanced Computer Science, vol. 3, no. 1, pp. 44-50, January 2013.; [41] Jaehoon Yu, Ryusuke Miyamoto, Takao Onoye, ``Speed-Up of Cohog-Based Pedestrian Detection by Stochastic Sampling,'' 画像電子学会誌, vol. 42, no. 1, pp. 30-40, January 2013.; [42] Masahiro Nakanishi, Masahide Hatanaka, Takao Onoye, ``User Interface Management System for Home Appliance,'' 画像電子学会誌, vol. 42, no. 1, pp. 81-88, January 2013.; [43] M. Hatanaka, T. Homemoto, and T. Onoye, ``Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems,'' VLSI Design, vol. vol. 2013, Article ID 967370, 9 pages, 2013.; [44] T. Enami, T. Sato, and M. Hashimoto, ``Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2261--2271, December 2012.; [45] Y. Takai, M. Hashimoto, and T. Onoye, ``Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2220--2225, December 2012.; [46] S. Kimura, M. Hashimoto, and T. Onoye, ``A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2292--2300, December 2012.; [47] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, ``Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 2791--2795, December 2012.; [48] Ryusuke Endo, Yuichi Itoh, Kosuke Nakajima, Kazuyuki Fujita, Fumio Kishino, ``Digital Signage Supporting Collaborative Route Planning in Real Commercial Establishment,'' ICIC Express Letters, vol. 6, no. 12, pp. 2967-2972, December 2012.; [49] M. Okada, T. Onoye, and W. Kobayashi, ``A Ray Tracing Simulation of Sound Diffraction Based on the Analytic Secondary Source Model,'' IEEE Trans. Audio, Speech and Language Processing , vol. 20, no. 9, pp. 2448-2460 , November 2012.; [50] 中島康祐, 伊藤雄一, 築谷喬之, 藤田和之, 高嶋和毅, 岸野文郎, ``FuSA2 Touch Display: 大画面毛状マルチタッチディスプレイ,'' 情報処理学会論文誌, vol. 53, no. 3, pp. 1069-1081, March 2012.; [51] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 20, no. 2, pp. 333--343, February 2012.; [52] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating NBTI-Induced Delay Degradation,'' IEICE Trans. Fundamentals, vol. E94-A, no. 12, pp. 2545-2553, December 2011.; [53] K. Shinkai, M. Hashimoto, and T. Onoye, ``Extracting Device-Parameter Variations with Ro-Based Sensors,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 12, pp. 2537--2544, December 2011.; [54] T. Okumura and M. Hashimoto, ``Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 10, pp. 1948--1953, October 2011.; [55] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Transactions on Nuclear Science, vol. 58, no. 4, pp. 2097--2102, August 2011.; [56] H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, ``An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion,'' IEEE Transactions on Circuits and Systems II, vol. 58, no. 5, pp. 299--303, May 2011.; [57] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. 93-A, no. 12, pp. 2399-2408, December 2010.; [58] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2417-2423, December 2010.; [59] S. Ninomiya and M. Hashimoto, ``Accuracy Enhancement of Grid-Based Ssta by Coefficient Interpolation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2441--2446, December 2010.; [60] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in Sta under Dynamic Power Supply Noise,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2447--2455, December 2010.; [61] M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``3D Sound Rendering for Multiple Sound Sources Based on Fuzzy Clustering,'' IEICE Trans. Fundamentals, vol. E93-A, no. 11, pp. 2163-2172, November 2010.; [62] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 18, no. 7, pp. 1118--1129, July 2010.; [63] Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa, ``Application Design of Multi-Standard Decoder on Media-Centric Reconfigurable Architecture,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. J93-A, no. 6, pp. 397-413, June 2010.; [64] Kenji WATANABE, Toshimitsu TATSUKA, Masahide HATANAKA, Takao ONOYE, ``A Room Layout Estimation Method for Indoor Localization System,'' Journal of Signal Processing, vol. 14, no. 3, pp. 231-242, May 2010.; [65] K. Shinkai, M. Hashimoto, and T. Onoye, ``Prediction of Self-Heating in Short Intra-Block Wires,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 3, pp. 583-594, March 2010.; [66] T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, ``Impact of Self-Heating in Wire Interconnection on Timing,'' IEICE Trans. on Electronics, vol. E93-C, no. 3, pp. 388--392, March 2010.; [67] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, ``Modeling the Overshooting Effect for Cmos Inverter Delay Analysis in Nanometer Technologies,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 29, no. 2, pp. 250--260, February 2010.; [68] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3094-3102, December 2009.; [69] T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, ``An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3016--3023, December 2009.; [70] 廣本正之, 筒井弘, 越智裕之, 小佐野智之, 石川憲洋, 中村行宏, ``Media Streaming System with Dynamic Rate Control for High Speed Mobile Networks,'' 情報処理学会論文誌, vol. 50, no. 10, pp. 2532-2542, October 2009.; [71] A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto, ``Interconnect Modeling: a Physical Design Perspective (Invited),'' IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1840--1851, September 2009.; [72] M. Hatanaka, T. Tatsuka, K. Watanabe, T. Onoye, ``Location Estimation with Transmission Attenuation in Home Network,'' IPSJ Journal, vol. 50, no. 8, p. 1835–1844, August 2009.; [73] Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, and Yukihiro Nakamura, ``Efficient Memory Organization Framework for Jpeg2000 Entropy Codec,'' IEICE Trans. Fundamentals, vol. E92-A, no. 8, pp. 1970-1977, August 2009.; [74] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform,'' IEEE Journal of Solid-State Circuits, vol. 44, no. 6, pp. 1745--1755, June 2009.; [75] 増崎隆彦, 筒井弘, 尾上孝雄, 水野雄介, 佐々木元, 中村行宏, ``A Jpeg2000 Codec System Architecture for Single Tile Processing,'' Journal of IIEEJ, vol. 38, no. 3, pp. 296-304, May 2009.; [76] T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 4, pp. 541-553, April 2009.; [77] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, ``Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. 92-A, no. 4, pp. 990--997, April 2009.; [78] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Trans. on Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.; [79] Takahiko Masuzaki, Hiroshi Tsutsui, Quang Minh Vu, Takao Onoye, and Yukihiro Nakamura, ``JPEG2000 High-Speed SNR Progressive Decoding Scheme,'' International Journal of Computer Science and Network Security, vol. 9, no. 1, pp. 62-68, January 2009.; [80] Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa, ``Area-Efficient Reconfigurable Architecture for Media Processin,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3651-3662, December 2008.; [81] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3461-3464, December 2008.; [82] S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3481-3487, December 2008.; [83] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, ``Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3474-3480, December 2008.; [84] R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, ``Implementation of Multi-Agent Object Attention System Based on Biologically Inspired Attractor Selection,'' IEICE Trans. Fundamentals, vol. E91-A, no. 10, October 2008.; [85] 渡辺慎吾, 橋本昌宜, 佐藤寿倫, ``タイミング歩留まり改善を目的とする演算器カスケーディング,'' 情報処理学会論文誌コンピューティングシステム, vol. 1, no. 2, pp. 12--21, August 2008.; [86] Nobuyuki Iwanaga, Tomoya Matsumura, Akihiro Yoshida, Wataru Kobayashi, and Takao Onoye, ``Embedded System Implementation of Sound Localization in Proximal Region,'' IEICE Trans. Fundamentals, vol. E91-A, no. 3, pp. 763-771, March 2008.; [87] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects,'' IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718-728, March 2008.; [88] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' IEICE Trans. on Information and Systems , vol. E91-D, no. 3, pp. 655--660, March 2008.; [89] 高橋真吾, 築山修治, 橋本昌宜, 白川功, ``液晶ディスプレイ用サンプリング回路におけるサンプリングパルスとトランジスタサイズの最適設計手法,'' 電子情報通信学会論文誌A, vol. J91-A, no. 3, pp. 373-382, March 2008.; [90] M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of LCD Driver Circuit for Technology Migration,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2712--2717, December 2007.; [91] M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2661-2668, December 2007.; [92] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872, October 2007.; [93] K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Automatic Filter Design for 3-D Sound Movement in Embedded Applications,'' In Acoustical Science and Technology, vol. 28, no. 4, pp. 219-229, July 2007.; [94] M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, ``Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4,'' International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.; [95] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling,'' IEICE Trans. on Electronics, vol. E90-C, no. 6, pp. 1267-1273, June 2007.; [96] Ryusuke Miyamoto, Jaehoon Yu, Hiroshi Tsutsui, Yukihiro Nakamura, ``Highly Accurate Stereo Matching Processor Based on Variable Window Approach,'' Journal of IIEEJ, vol. 36, no. 3, pp. 210-218, May 2007.; [97] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise　and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect,'' In IEICE Trans. on Fundamentals of Electronics,　Communications and Computer Sciences, vol. E90-A, no. 4, pp. 724--731, April 2007.; [98] K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Efficient 3-D Sound Movement with Time-Varying Iir Filters,'' In IEICE Trans. Fundamentals, vol. E90-A, no. 3, pp. 618--625, March 2007.; [99] K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, ``An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control,'' In IEEE Trans. Consumer Electronics, vol. 53, no. 1, pp. 124--130, February 2007.; [100] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538--3545, December 2006.; [101] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560--3568, December 2006.; [102] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538-3545, December 2006.; [103] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.; [104] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.; [105] T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3491-3499, December 2006.; [106] T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M Hashimoto, ``Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3666-3670, December 2006.; [107] 小谷章夫, 種村嘉高, 密山幸男, 朝井宣実, 中村安久, 尾上孝雄, ``Potential Energy-Based Center of Gravity Evaluation of　Characters,'' Journal of the Institute of Image Elecgtronics　Engineerings of Japan, vol. 35, no. 4, pp. 296--305, July 2006.; [108] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa, ``Effectiveness of Ground Plane and Shield Wires for Reduction of Coupling Capacitance and Simplification of Capacitance Estimation in System on Panel Circuits,'' IPSJ Trans., vol. 47, no. 6, pp. 1665--1673, June 2006.; [109] G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa, ``Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation,'' In IEICE Trans. Fundamentals, vol. E89-A, no. 4, pp. 941--949, April 2006.; [110] H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Framework for JPEG2000 System Architecture,'' In Journal of Intelligent Automation and Soft Computing, vol. 13, no. 3, pp. 331--343, March 2006.; [111] Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network,'' IEEE Transactions on Consumer Electronics, vol. 52, no. 1, pp. 81--86, February 2006.; [112] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``W-CDMA Channel Codec by Configurable Processors,'' In Intelligent Automation and Soft Computing, vol. 12, no. 3, pp. 317--29, 2006.; [113] M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3375-3381, December 2005.; [114] A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3564-3572, December 2005.; [115] T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment for Minimizing Supply Voltage Drop,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3429-3436, December 2005.; [116] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3382-3389, December 2005.; [117] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, , Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, ``Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3453-3462, December 2005.; [118] G. Fujita, T. Onoye, I. Shirakawa, ``VLSI Implementation of High Accuracy Motion Estimation Core for MPEG-4,'' IEICE Trans. Fundamentals, vol. J88-A, no. 11, pp. 1282-1382, November 2005.; [119] A. Kosaka, H. Okuhata, T. Onoye, and I. Shirawaka, ``Desing of Ogg Vorbis Decoder System for Embedded Platform,'' IEICE Trans. Fundamentals, vol. E88-A, no. 8, pp. 2124--2130, August 2005.; [120] K. Tsujino, K. Furuya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, ``Design of Realtime 3-D Sound Processing System,'' In IEICE Trans. Fundamentals, vol. E88-A, no. 8, pp. 2124--2130, August 2005.; [121] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa, ``Interconnect Capacitance Extraction for System LCD Circuits,'' IPSJ Trans., vol. 46, no. 6, pp. 1395--1403, June 2005.; [122] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp. 899-906, April 2005.; [123] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E88-A, no. 4, pp. 885-891, April 2005.; [124] T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' IEICE Trans. on Electronics, vol. E88-C, no. 3, pp. 437-444, March 2005.; [125] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function,'' IEEE Transactions on Consumer Electronics, vol. 51, no. 1, pp. 262--267, February 2005.; [126] M. Hatanaka, T. Masaki, M. Okada, and K. Murakami, ``VLSI Architecture of PSK Demodulator for Digital BS and CS Broadcasting,'' Proc. The Journal Of The Institute Of Image Information And Television Engineers, vol. 59, no. 1, pp. 69--76, January 2005.; [127] M. Hashimoto and H. Onodera, ``Crosstalk Noise Optimization by Post-Layout Transistor Sizing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E87-A, no. 12, pp. 3251-3257, December 2004.; [128] M. Hashimoto, Y. Yamada, and H. Onodera, ``Equivalent Waveform Propagation for Static Timing Analysis,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 23, no. 4, pp. 498-508, April 2004.; [129] T. Okada, T. Uchida, T. Onoye, I. Shirakawa, ``Signal Processing Scheme for Next Generation GNSS Receiver and Its VLSI Implementation,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. J86-A, no. 12, pp. 1417--1425, December 2003.; [130] S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays,'' IEICE Trans. on Fundamentals, vol. E86-A, no. 12, pp. 2923--2932, December 2003.; [131] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``Implementation of Java Accelerator for High-Performance Embedded Systems,'' in IEICE Trans. Fundamentals, vol. E86-A, no. 12, pp. 3079--3088, December 2003.; [132] H. -S. Song, H. Okada, G. Fujita, T. Onoye, I. Shirakawa, ``Hybrid Error Concealment Algorithm for MPEG-4 Video Coding,'' The Journal of the Institute of Image Electronics of Japan, vol. 32, no. 5, pp. 609--620, September 2003.; [133] A. Kotani, N. Koyama, Y. Mitsuyama, T. Onoye, ``Center of Gravity and Readability on "LCFONT" for Low Resolution Display,'' The Journal of the Institute of Image Electronics of Japan, vol. 32, no. 5, pp. 621--628, September 2003.; [134] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources,'' in IEEE Trans. on Consumer Electronics, vol. 49, no. 3, pp. 737--741, August 2003.; [135] T. Okamoto, T. Yuasa, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Tools and Trial Design for Pca-Chip2,'' In IEICE Trans. Information and Systems,, vol. E86-D, no. 5, pp. 868--871, May 2003.; [136] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa, ``Object Sharing Scheme for Heterogeneous Environment,'' in IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 4, pp. 813--821, April 2003.; [137] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm,'' Journal of Circuits, Systems and Computers, vol. 12, no. 1, pp. 55-73, February 2003.; [138] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Performance Estimation at Architecture Level for Embedded Systems,'' IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 12, pp. 2636--2644, December 2002.; [139] Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, ``Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Communications, vol. E85-B, no. 10, pp. 2032--2043, October 2002.; [140] H. Okada, H.-S. Song, G. Fujita, T. Onoye, I. Shirakawa, ``Application of Digital Watermarking to MPEG-4 Bitstream Error Detection,'' The Journal of the Institute of Image Electronics of Japan, vol. 31, no. 5, pp. 900--908, September 2002.; [141] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Detection by Digital Watermarking for MPEG-4 Video Coding,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 6, pp. 1281--1288, June 2002.; [142] T. Song, G. Fujita, T. Onoye, I. Shirakawa, ``Low Power Implementation of H.263 Version 2 Codec Core Dedicated to Mobile Computing,'' IPSJ Trans., vol. 43, no. 4, pp. 1161--1170, May 2002.; [143] M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, ``Code Efficiency Evaluation for Embedded Processors,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 4, pp. 811--818, April 2002.; [144] Roberto Y. Omaki, Gen Fujita, Takao Onoye, and Isao Shirakawa, ``An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E85-A, no. 3, pp. 703--713, March 2002.; [145] Hiroshi Tsutsui, Akihiko Tomita, Shigenori Sugimoto, Kazuhisa Sakai, Tomonori Izumi, Takao Onoye, and Yukihiro Nakamura, ``Lut-Array-Based Pld and Synthesis Approach Based on Sum of Generalized Complex Terms Expression,'' IEICE Trans. Fundamentals, vol. E84-A, no. 11, pp. 2681-2689, November 2001.; [146] S. Tani, I. Shirakawa, ``Impedance Analysis for Power Distribution Planes in Multilayer Printed Circuit Boards,'' Journal of JIEP(Japan Institute of Electronics Packaging), vol. 4, no. 5, pp. 378--385, August 2001.; [147] W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' IEICE(The Institute of Electronics, Information and Communication Engineers) Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1423--1430, June 2001.; [148] T. Watanabe and N. Ishiura, ``Resister Constraint Analysis to Minimize Spill Code for Application Specific DSPs,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1541--1544, June 2001.; [149] K. Kawamoto, K. Kohno, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A 25kV ESD Proof LDMOSFET with a Turn-On Discharge MOSFET,'' IEICE Trans. Electron, vol. E84-C, no. 6, pp. 823--831, June 2001.; [150] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A Novel Dynamically Reconfigurable Hardware-Based Cipher,'' Trans. of IPSJ(Information Processing Society of Japan), vol. 42, no. 4, pp. 958--966, April 2001.; [151] K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, ``A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS,'' The Japan Society of Applied Physics, vol. 40, no. 4B, pp. 2891--2896, April 2001.; [152] K. Kawamoto, H. Yamaguchi, H. Himi, S. Fujino, and I. Shirakawa, ``A 200 V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays,'' IEICE Trans. Electron, vol. E84-C, no. 2, pp. 260--266, February 2001.; [153] M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, ``Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes,'' IEICE Trans. Fundamentals, vol. E83-A, no. 12, pp. 2456--2463, December 2000.; [154] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic,'' Trans. of IPSJ, vol. 41, no. 4, pp. 899--907, April 2000.; [155] K. Matsumura, M. Furuie, G. Fujita, T. Masaki, I. Shirakawa, H. Inada, ``LSI Implementation of Wireless Data System Controller for MedecalCares,'' IPSJ Trans., ., vol. 41, no. 4, pp. 962--969, April 2000.; [156] M. Hatanaka, T. Masaki, T. Onoye, and K. Murakami, ``VLSI Architecture of Switching Control for AAL Type2 Switch,'' IEICE Trans. Fundamentals, vol. E83--A, no. 3, pp. 435--441, March 2000.; [157] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Scheme of NMOS 4-Phase Dynamic Logic,'' IEICE Trans. Electron., vol. E82--C, no. 9, pp. 1772--1776, September 1999.; [158] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``An Architecture of a Matrix-Vector Multiplier Dedicated to Video Decoding and Three-Dimensional Computer Graphics,'' IEEE Trans. Circuits and Systems for Video Technology, vol. 9, no. 2, pp. 306--314, March 1999.; [159] A. Nagao, I. Shirakawa, and T. Kambe, ``A Layout Approach to Monolithic Microwave IC,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1262--1272, December 1998.; [160] Masayuki Yamaguchi, Nagisa Ishiura, and Takashi Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal DSP Architecture,'' IEICE Trans. Fundamentals, vol. E81-A, no. 12, pp. 2630--2639, December 1998.; [161] M. H. Miki, G. Fujita, T. Onoye, I. Shirakawa, ``Low Power Implementation of H.263 Codec Core Dedicated to Mobile Computing,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. J81-A, no. 10, pp. 1352--1361, October 1998.; [162] A. Nagao, T. Sawa, Y. Shigehiro, I. Shirakawa, T. Kambe, ``A New Approach to Rectangle-Packing,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. J81-A, no. 10, pp. 1362--1371, October 1998.; [163] H. Okuhata, Morgan H. Miki, T. Onoye, and I. Shirakawa, ``A Low-Power DSP Core Architecture for Low Bitrate Speech Codec,'' IEICE Trans. Fundamentals, vol. E81-C, no. 8, pp. 1616--1621, August 1998.; [164] K. Kimura, H. Okuhata, T. Onoye, I. Shirakawa, T. Kiyohara, T. Sagishima, ``Control Method of Data Cache for Multithreaded Processor,'' The Journal of The Institute of Image Information and Television Engineers, vol. 52, no. 5, pp. 742--749, May 1998.; [165] G. Fujita, T. Onoye, and I. Shirakawa, ``A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding,'' IEICE Trans. Electronics, vol. E81-C, no. 5, pp. 702--707, May 1998.; [166] T. Masaki, Y. Nakatani, T. Onoye, N. Yamai, and K. Murakami, ``Voice Communication on Multimedia ATM Network Using Shared VCI Cell,'' IEICE Trans. Communications, vol. E81-B, no. 2, pp. 340-346, February 1998.; [167] I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 12, pp. 2589-2599, December 1997.; [168] M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1853-1860, October 1997.; [169] S. Yano and N. Ishiura, ``Embedded Memory Array Testing Using a Scannable Configuration,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1934-1944, October 1997.; [170] N. Shimizu, S. Koyama, H. Ono, K. Miyashita, H. Kondo, Y. Mizuta, ``Field Experiments and Data Processing for Continuous Measurements by GPS Displacement Monitoring System,'' Shigen-to-Sozai, vol. 113, no. 7, pp. 549-554, July 1997.; [171] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, I. Shirakawa, ``A Low-Power Consumption Architecture for Embedded Processors,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. J80-A, no. 5, pp. 765-771, May 1997.; [172] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication,'' J. Circuits, Systems, and Computers, vol. 7, no. 5, pp. 441-457, May 1997.; [173] H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, ``A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication,'' J. Circuits, Systems, and Computers, vol. 7, no. 5, pp. 483-494, May 1997.; [174] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Voice and Telephony Over ATM for Multimedia Network Using Shared VCI Cell,'' J. Circuits, Systems, and Computers, vol. 7, no. 2, pp. 93-110, April 1997.; [175] S. Yano, K. Akagi, H. Inohara, and N. Ishiura, ``Application of Full Scan Design to Embedded Memory Arrays,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 3, March 1997.; [176] H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, ``ASK Digital Demodulation Scheme for Noise Immune Infrared Data Communication,'' ACM Wireless Networks, no. 3, pp. 121-129, 1997.; [177] K. Okada, S. Morikawa, S. Takeuchi, and I. Shirakawa, ``A High Performance Multiplier and Its Application to an FIR Filter Dedicated to Digital Video Transmission,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E79-A, no. 12, pp. 2106-2111, December 1996.; [178] 矢野政顕, 石浦菜岐佐, ``メモリアレーを含む順序回路へのスキャンパス方式適用,'' 電子情報通信学会論文誌, vol. J79-D-I, no. 12, pp. 1055-1062, December 1996.; [179] 近藤仁志, M. E. Cannon, 清水則一, 中川浩二, ``GPSによる地盤変位モニタリングシステムの開発,'' 土木学会論文誌, no. 546/VI-32, pp. 157-168, September 1996.; [180] Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``Automatic Layout Recycling Based on Layout Description and Linear Programming,'' in Proc. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp. 959-967, August 1996.; [181] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai, ``Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@{hl},'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E79-A, no. 8, pp. 1210-1216, August 1996.
International Conference: [1] Qiaochu Zhao, Ittetsu Taniguchi, Makoto Nakamura, and Takao Onoye, ``{An Efficient Parts Counting Method Based on Intensity Distribution Analysis for Industrial Vision Systems},'' In The 21st Workshop on Synthesis And System Integration of Mixed Information techologies, March 2018. (Kunibiki Messe, Matsue, Japan); [2] S. Negoro, K. Maekawa, D. Sukezane, A. Shibata, I. Taniguchi, and H. Tomiyama, ``Measurement and Modeling of Quadcopter Energy with Ros,'' In Proc. The 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018), pp. 169--173, March 2018. (Matsue, Japan); [3] R. Shirai, Y. Itoh, T. Fukamachi, M. Yamashita, and T. Onoye, ``Optrod: Operating Multiple Various Actuators Simultaneously by Projected Images,'' In SIGGRAPH Asia 2017 Emerging Technologies, no. 11, pp. 1-2, November 2017.; [4] K. Maekawa, S. Negoro, I. Taniguchi, and H. Tomiyama, ``Power Measurement and Modeling of Quadcopters on Horizontal Flight,'' In International Workshop on Computer Systems and Architectures (CSA) in conjunction with International Symposium on Computing and Networking (CANDAR), p. xxx--xxx (4 pages), November 2017. (Aomori, Japan); [5] R. Shirai, T. Hirose, and M. Hashimoto, ``{Dedicated Antenna Less Power Efficient Ook Transmitter for Mm-Cubic Iot Nodes},'' Proceedings of the 47th European Microwave Conference (EuMC), pp. 101--104, October 2017.; [6] M. Hashimoto, R. Shirai, Y. Itoh, and T. Hirose, ``Toward Real-Time 3d Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited),'' Proceedings of IEEE International Conference on ASIC, pp. 1087--1091, October 2017.; [7] T. Yamamoto, H. Tomiyama, I. Taniguchi, S. Yamashita, and Y. Hara-Azumi, ``Systematic Design of Approximate Array Multipliers with Different Accuracy,'' In International Workshop on Highly Efficient Neural Networks Design (HENND) in conjunction with ESWEEK, p. xxx--xxx (4 pages), October 2017. (Seoul, Korea); [8] Yusuke Sakumoto and Ittetsu Taniguchi, ``Evaluation of MCMC-Based Autonomous Decentralized Mechanism of Energy Interchange in Practical Scenario with Generation Fluctuation,'' In 22nd IEEE International Conference on Emerging Technologies & Factory Automation (ETFA2017), p. xxx--xxx (5 pages), September 2017. (Limassol, Cyprus); [9] R. Shirai, J. Kono, T. Hirose, and M. Hashimoto, ``Near-Field Dual-Use Antenna for Magnetic-Field Based Communication and Electrical-Field Based Distance Sensing in Mm^3-Class Sensor Node,'' Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 124--127, May 2017.; [10] Kazuki Hirosue, Shohei Ukawa, Yuichi Itoh, Takao Onoye, and Masanori Hashimoto, ``Gpgpu-Based Highly Parallelized 3d Node Localization for Real-Time 3d Model Reproduction,'' In Proceedings of the 22nd International Conference on Intelligent User Interfaces 2017 (IUI '17), pp. 173-178, March 2017.; [11] Yuki Tsujimoto, Yuichi Itoh, and Takao Onoye, ``Ketsuro-Graffiti: an Interactive Dislplay with Water Condensation,'' In Proceedings of ACM International Conference on Interactive Surfaces and Spaces 2016 (ISS 2016), pp. 49-55, November 2016.; [12] Y. Masuda, M. Hashimoto, and T. Onoye, ``Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 28-35, March 2016.; [13] R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, ``Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.; [14] U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, and B. Li, ``Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited),'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 705--711, January 2016.; [15] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi Author(s) in English , ``A Novel Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch (2v-1cas) for Nonvolatile Crossbar Switch with Multiple Fan-Outs,'' Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 32--35, December 2015.; [16] Y. Masuda, M. Hashimoto, and T. Onoye, ``Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise,'' In Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 315-322, November 2015.; [17] R. Doi, M. Hashimoto, and T. Onoye, ``An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication,'' IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), November 2015.; [18] E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, ``Design of Generic Hardware for Soft Cascade-Based Linear Svm Classification,'' In International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 257-262, November 2015.; [19] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, ``Stochastic Timing Error Rate Estimation under Process and Temporal Variations,'' In Proceedings of International Test Conference (ITC), October 2015.; [20] Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, and M. Hashimoto, ``A Wireless Power Transfer System for Small-Sized Sensor Applications,'' Proceedings of International Conference on Solid State Devices and Materials (SSDM), pp. 154--155, September 2015.; [21] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, ``Neutron-Induced Seu and Mcu Rate Characterization and Analysis of Sotb and Bulk Srams at 0.3v Operation,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.; [22] M. Ueno, M. Hashimoto, and T. Onoye, ``Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization,'' Proceedings of International On-Line Testing Symposium (IOLTS), pp. 188--193, July 2015.; [23] M. Hashimoto, ``Run-Time Performance Adaptation: Opportunities and Challenges (Invited),'' Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), June 2015.; [24] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, ``Impact of Package on Neutron Induced Single Event Upset in 20 Nm Sram,'' Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.; [25] T. Uemura and M. Hashimoto, ``Investigation of Single Event Upset and Total Ionizing Dose in Feram for Medical Electronic Tag,'' Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.; [26] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft Error Immune Latch Design for 20 Nm Bulk Cmos,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2015.; [27] S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, and T. Onoye, ``3d Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method,'' Proceedings of Virtual Reality Conference (VR), March 2015.; [28] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, ``Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 731--736, January 2015.; [29] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 14--15, January 2015.; [30] T. Amaki, M. Hashimoto, and T. Onoye, ``An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 4--5, January 2015.; [31] Yuki Tsujimoto, Yuichi Itoh, and Takao Onoye, ``Ketsuro-Graffiti: a Canvas with Computer Generated Water Condensation,'' In SIGGRAPH Asia 2015 Emerging Technologies, pp. 15:1--15:2, 2015.; [32] M. Hashimoto, ``Stochastic Verification of Run-Time Performance Adaptation with Field Delay Testing (Invited),'' Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 751--754, November 2014.; [33] M. Hashimoto, ``Opportunities and Verification Challenges of Run-Time Performance Adaptation (Invited),'' Proceedings of Asian Test Symposium (ATS), pp. 248--253, November 2014.; [34] Yohei Miyazaki, Yuichi Itoh, Yuki Tsujimoto, Masahiro Ando, and Takao Onoye, ``Ketsuro-Graffiti: Water Condensation Display,'' In ACE '14 Proceedings of the 11th Conference on Advances in Computer Entertainment Technology, November 2014.; [35] Kosuke Tomita, Masahide Hatanaka, and Takao Onoye, ``An Approach to GPU Implementation of OFDM Transceiver Using Dynamic Spectrum Access,'' In 2014 International Workshop on Smart Info-Media Systems in Asia, SISA 2014, October 2014.; [36] M. Hashimoto, ``Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective (Invited),'' Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2014.; [37] A. Iokibe, M. Hashimoto, and T. Onoye, ``Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground,'' Proceedings of International Conference on Sensing Technology (ICST), pp. 188--193, September 2014.; [38] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Optimizing Well-Configuration for Minimizing Single Event Latchup,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.; [39] R. Harada, S. Hirokawa, and M. Hashimoto, ``Measurement of Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4 V Srams,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.; [40] T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, ``Preventing Single Event Latchup with Deep P-Well on P-Substrate,'' Proceedings of International Reliability Physics Symposium (IRPS), June 2014.; [41] M. Ueno, M. Hashimoto, and T. Onoye, ``Trace-Based Fault Localization with Supply Voltage Sensor,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2014.; [42] C.Siriteanu, A.Takemura, S.D. Blostein, S.Kuriki, and H.Shin, ``Convergence Analysis of Performance-Measure Expressions for Mimo Zf under Rician Fading,'' Australian Communications Theory Workshop, AUSCTW'14, Sydney, Australia, pp. 114-119 , February 2014.; [43] Masahiro Ando, Yuichi Itoh, Toshiki Hosoi, Kazuki Takashima, Kosuke Nakajima, and Yoshifumi Kitamura, ``Stackblock: Block-Shaped Interface for Flexible Stacking,'' In Proc. of UIST, pp. 41-42, 2014.; [44] Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, and Takao Onoye, ``Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design,'' In ReConFig, December 2013.; [45] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 313-316, November 2013.; [46] T. Amaki, M. Hashimoto, and T. Onoye, ``A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction,'' In Proceedings of Asian Solid-State Circuits Conference (A-SSCC), pp. 133-136, November 2013.; [47] S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, ``Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 107-114, November 2013. (San Jose); [48] Kosuke Nakajima, Yuichi Itoh, Yusuke Hayashi, Kazuaki Ikeda, Kazuyuki Fujita, and Takao Onoye, ``Emoballoon: a Balloon-Shaped Interface Recognizing Social Touch Interactions,'' In Proceedings of 10th International Conference on Advances in Computer Entertainment Technology, pp. 182-197, November 2013.; [49] J. Kono, M. Hashimoto, and T. Onoye, ``Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm^3 Antenna,'' Proceedings of Asia-Paciﬁc Microwave Conference (APMC), pp. 1121--1123, November 2013.; [50] R. Harada, M. Hashimoto, and T. Onoye, ``Nbti Characterization Using Pulse-Width Modulation,'' IEEE/ACM Workshop on Variability Modeling and Characterization, November 2013.; [51] Simon Voelker, Kosuke Nakajima, Christian Thoresen, Yuichi Itoh, Kjell Ivar Øvergård, and Jan Borchers, ``Pucs: Detecting Transparent, Passive Untouched Capacitive Widgets on UnmodiﬁEd Multi-Touch Displays,'' In Adjunct Publication of the 26th Annual ACM Symposium on User Interface Software and Technology, pp. 1-2, October 2013.; [52] Simon Voelker, Kosuke Nakajima, Christian Thoresen, Yuichi Itoh, Kjell Ivar Øvergård, and Jan Borchers, ``Pucs Demo: Detecting Transparent, Passive Untouched Capacitive Widgets,'' In Proceedings of the 2013 ACM International Conference on Interactive Tabletops and Surfaces, pp. 325-328, October 2013.; [53] Simon Voelker, Kosuke Nakajima, Christian Thoresen, Yuichi Itoh, Kjell Ivar Øvergård, and Jan Borchers, ``Pucs: Detecting Transparent, Passive Untouched Capacitive Widgets on UnmodiﬁEd Multi-Touch Displays,'' In Proceedings of the 2013 ACM International Conference on Interactive Tabletops and Surfaces, pp. 101-104, October 2013.; [54] M. Hashimoto, ``Soft Error Immunity of Subthreshold Sram (Invited),'' Proceedings of IEEE International Conference on ASIC, pp. 91--94, October 2013.; [55] Y.Fukuhara, A.Yamada, and T.Onoye, ``An Image Compression Method for Frame Memory Size Reduction Using Local Feature of Images,'' In The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2013), pp. 288-289, October 2013.; [56] Yohei Kojima, Kazuma Aoyama, Yuichi Itoh, Kazuyuki Fujita, Taku Fujimoto, and Kosuke Nakajima, ``Polka Dot: the Garden of Water Spirits,'' In ACM SIGGRAPH 2013 Posters, July 2013. (Article No. 47); [57] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Scaling Trend of Sram and Ff of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk Cmos Technology,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.; [58] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft-Error in Sram at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.; [59] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.; [60] T. Shinada, M. Hashimoto, and T. Onoye, ``Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes,'' Proceedings of International NEWCAS Conference, June 2013.; [61] M. Ueno, M. Hashimoto, and T. Onoye, ``Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures,'' Proceedings of Reconfigurable Architectures Workshop (RAW), pp. 301--305, May 2013.; [62] Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, and S. Nassif, ``Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator,'' Proceedings of IEEE European Test Symposium (ETS), pp. 106--111, May 2013.; [63] Kazuyuki Fujita, Yuichi Itoh, Kazuki Takashima, Kosuke Nakajima, Yusuke Hayashi, and Fumio Kishino, ``Ambient Party Room: a Room-Shaped System Enhancing Communication for Parties Or Gatherings,'' In Proceedings of the 2nd International Workshop on Ambient Information Technologies, pp. 1-4, March 2013.; [64] Kosuke Nakajima, Yuichi Itoh, Yusuke Hayashi, Kazuaki Ikeda, Kazuyuki Fujita, and Takao Onoye, ``Emoballoon: a Balloon-Shaped Interface Recognizing Social Touch Interactions,'' In Proceedings of the 2nd International Workshop on Ambient Information Technologies, pp. 13-16, March 2013.; [65] M. Hashimoto, ``Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (Invited),'' China Semiconductor Technology International Conference (CSTIC), pp. 1079--1084, March 2013.; [66] Jin Kono, Masanori Hashimoto, Takao Onoye, ``Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm3 Antenna,'' Microwave Conference Proceedings (APMC), 2013 Asia-Pacific, pp. 1121-1123, 2013.; [67] Yohei Kojima, Yuichi Itoh, Taku Fujimoto, and Kosuke Nakajima, ``Polka Dot – the Garden of Water Spirits,'' In SIGGRAPH Asia 2013 Emerging Technologies, p. 15, 2013.; [68] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices,'' Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012.; [69] Yuya Iwasaki, Masahide Hatanaka, and Takao Onoye, ``Performance Improvement of Channel Estimation for Ofdm Baseband Transceiver with Dynamic Subcarrier Selection,'' In The First Asian Conference on Information Systems,ACIS 2012, December 2012.; [70] Kazutaka Takeuchi, Ryusuke Miyamoto, and Takao Onoye, ``High-Speed Multiview Video Decoding for Embedded System,'' In The First Asian Conference on Information Systems, ACIS 2012, December 2012.; [71] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Converter Based on Minimax Sampling,'' Proceedings of International SoC Design Conference (ISOCC), p. 120 -- 123 , November 2012.; [72] Kazuki Takashima, Yusuke Hayashi, Kosuke Nakajima, and Yuichi Itoh, ``Cup-Embedded Information Device for Supporting Interpersonal Communication,'' In Proceedings of Joint Virtual Reality Conference of ICAT, EGVE and EuroVR, pp. 19-20, October 2012.; [73] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of Nbti-Induced Pulse-Width Modulation on Set Pulse-Width Measurement,'' Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.; [74] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.; [75] Ryusuke Endo, Yuichi Itoh, Kosuke Nakajima, Kazuyuki Fujita, and Fumio Kishino, ``Planning-Capable Digital Signage System Using Multi-Touch Display,'' In Proceedings of The 10th Asia Pacific Conference on Computer Human Interaction (APCHI2012), vol. 2, pp. 545-554, August 2012.; [76] Kosuke Nakajima, Yuichi Itoh, Yusuke Hayashi, Kazuaki Ikeda, Kazuyuki Fujita, and Takao Onoye, ``Emoballoon,'' In Proceedings of The 10th Asia Pacific Conference on Computer Human Interaction (APCHI2012), vol. 2, pp. 681-682, August 2012.; [77] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, ``Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Nuclear and Space Radiation Effects Conference, July 2012.; [78] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2012.; [79] K. Kiyokawa, M. Hatanaka, K. Hosoda, M. Okada, H. Shigeta, Y. Ishihara, F. Ooshita, H. Kakugawa, S. Kurihara, and K. Moriyama, ``Owens Luis - a Context-Aware Multi-Modal Smart Office Chair in an Ambient Environment,'' In The 1st International Workshop on Ambient Information Technologies (AMBIT-2012), Orange County, CA, USA, March 2012.; [80] H. Shigeta, J. Nakase, Y. Tsunematsu, K. Kiyokawa, M. Hatanaka, K. Hosoda, M. Okada, Y. Ishihara, F. Ooshita, H. Kakugawa, S. Kurihara, and K. Moriyama, ``Implementation of a Smart Office System in an Ambient Environment,'' In The 1st International Workshop on Ambient Information Technologies (AMBIT-2012), Orange County, CA, USA, March 2012.; [81] K. Watanabe, G. Fujita, T. Homemoto, and R. Hashimoto, ``A High-Speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator,'' The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 6-10, March 2012.; [82] Kosuke Nakajima, Yuichi Itoh, Takayuki Tsukitani, Kazuyuki Fujita, Kazuki Takashima, Yoshifumi Kitamura, and Fumio Kishino, ``Fusa2 Touch Display: Furry and Scalable Multi-Touch Display,'' In Proceedings of The 1st International Workshop on Ambient Information Technologies, pp. 35-36, March 2012.; [83] Yusuke Hayashi, Yuichi Itoh, Kazuki Takashima, Kazuyuki Fujita, Kosuke Nakajima, Ikuo Daibo, and Takao Onoye, ``Cup-Le: a Cup-Shaped Device for Conversational Experiment,'' In Proceedings of the 1st International Workshop on Ambient Information Technologies, pp. 36-37, March 2012.; [84] Kazuyuki Fujita, Yuichi Itoh, Hiroyuki Ohsaki, Naoaki Ono, Keiichiro Kagawa, Kazuki Takashima, Sho Tsugawa, and Kosuke Nakajima, ``Ambient Suite: Room- Shaped Information Environment for Interpersonal Communication,'' In Proceedings of the 1st International Workshop on Ambient Information Technologies, pp. 18-21, March 2012.; [85] S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 283--289, February 2012.; [86] Takashi Nakamae, Akihisa Yamada, Masayuki Yamaguchi, and Takao Onoye, ``A Near-Lossless Image Compression Method Using Adaptive Variable Length Coding,'' In International Conference on Embedded Systems and Intelligent Technology, January 2012.; [87] K. Kiyokawa, M. Hatanaka, K. Hosoda, M. Okada, H. Shigeta, Y. Ishihara, F. Ooshita, H. Kakugawa, S. Kurihara, and K. Moriyama, ``Owens Luis - a Proposal of a Smart Office Chair in an Ambient Environment,'' In The 21st International Conference on Artificial Reality and Telexistence (ICAT 2011), Osaka, Japan, November 2011.; [88] Kazuyuki Fujita, Yuichi Itoh, Hiroyuki Ohsaki, Naoaki Ono, Keiichiro Kagawa, Kazuki Takashima, Sho Tsugawa, Kosuke Nakajima, Yusuke Hayashi, and Fumio Kishino, ``Ambient Suite: Enhancing Communication among Multiple Participants,'' In Proceedings of the International Conference on Advances in Computer Entertainment Technology , pp. 25:1-25:8, November 2011.; [89] Kosuke Nakajima, Yuichi Itoh, Takayuki Tsukitani, Kazuyuki Fujita, Kazuki Takashima, Yoshifumi Kitamura, and Fumio Kishino, ``Fusa2 Touch Display: Furry and Scalable Multi-Touch Display,'' In Proceedings of ACM International Conference on Interactive Tabletops and Surfaces 2011, pp. 35-44, November 2011.; [90] Kosuke Nakajima, Yuichi Itoh, Takayuki Tsukitani, Kazuyuki Fujita, Kazuki Takashima, Yoshifumi Kitamura, and Fumio Kishino, ``Fusa2 Touch Display,'' In Proceedings of ACM International Conference on Interactive Tabletops and Surfaces 2011, November 2011.; [91] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures,'' In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pp. 189-194, September 2011.; [92] Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, and Takao Onoye, ``Nbti Mitigation by Giving Random Scan-In Vectors during Standby Mode,'' In PATMOS2011, September 2011.; [93] Y. Takai, M. Hashimoto, and T. Onoye, ``Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2011.; [94] M. Okada, T. Onoye, and W. Kobayashi, ``A Ray Tracing Simulation of Sound Diffraction Based on Analytic Secondary Source Model,'' In 19th European Signal Processing Conference (EUSIPCO-2011), Barcelona, Spain, pp. 1653-1657, August 2011.; [95] M. Hashimoto and H. Fuketa, ``Adaptive Performance Compensation with On-Chip Variation Monitoring (Invited),'' In Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.; [96] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' In Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.; [97] T. Amaki, M. Hashimoto, and T. Onoye, ``An Oscillator-Based True Random Number Generator with Jitter Amplifier,'' In Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2011), pp. 725-728, May 2011.; [98] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing,'' In Proc. International Reliability Physics Symposium (IRPS), April 2011.; [99] S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 46--51, April 2011.; [100] K. Shinkai, M. Hashimoto, and T. Onoye, ``Extracting Device-Parameter Variations with Ro-Based Sensors,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 13--18, March 2011.; [101] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability,'' In IEEE Workshop on Silicon Errors in Logic - System Effects, March 2011.; [102] Tatsuo Maeno, Hiroshi Tsutsui, and Takao Onoye, ``Hardware Implementation of Real-Time Motion Adaptive Deinterlacing Based on Inpainting,'' In International Conference on Embedded Systems and Intelligent Technology, February 2011.; [103] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling,'' In Proc. International Workshop on Information Security Applications (WISA 2010), pp. 107-121, January 2011.; [104] T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 81-82, January 2011.; [105] K. Shinkai and M. Hashimoto, ``Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability,'' In Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 683-688, January 2011.; [106] M. Hashimoto, ``Run-Time Adaptive Performance Compensation Using On-Chip Sensors (Invited),'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 285--290, January 2011.; [107] M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, ``VLSI Design of OFDM Baseband Transceiver with Dynamic Spectrum Access,'' In Proc. of the 18th International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2010), pp. 329-332, December 2010.; [108] Y. Takai, M. Hashimoto, and T. Onoye, ``Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation,'' In Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 213--216, October 2010.; [109] Hideyuki Nakamura, Hiroshi Tsutsui, and Takao Onoye, ``Motion-Compensated Frame Interpolation Using Feature Tracking and Motion Segmentation,'' In International Workshop on Smart Info-Media Systems in Asia, September 2010.; [110] T. Okumura and M. Hashimoto, ``Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2010.; [111] L. M. Handaya, M. Okada, T. Onoye, and W. Kobayashi, ``Improvement of Frontal Localization with Complement of Multiple Delayed Sounds,'' 2010 International Workshop on Information Communication Technology, August 2010.; [112] K. Shinkai and M. Hashimoto, ``Self-Heating in Nano-Scale Vlsi Interconnects,'' In Proceedings of International Workshop on Information Communication Technology (ICT), pp. S-1-6, August 2010.; [113] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.; [114] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' In Proceedings of International Reliability Physics Symposium (IRPS), pp. 213--217, May 2010.; [115] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to Sso,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pp. 19--20, May 2010.; [116] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, ``A 16-Bit Risc Processor with 4.18pj/Cycle at 0.5v Operation,'' In Proceedings of IEEE COOL Chips, p. 190, April 2010.; [117] Yuki Kawamura, Yasutake Manabe, Takao Onoye, Kazuto Ohara, Hiroyuki Okada, and Ikuo Keshi, ``Implementation of Simultaneous Video Decoding on Multicore Processor,'' In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP 2010), March 2010.; [118] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 646-651, March 2010.; [119] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), March 2010.; [120] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 41-46, March 2010.; [121] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.; [122] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 361-362, January 2010.; [123] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in Sta under Dynamic Power Supply Noise,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), p. 775 -- 780, January 2010.; [124] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Soft Error Resilient Vlsi Architecture for Signal Processing,'' In Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 183--186, December 2009.; [125] Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, and Yukihiro Nakamura, ``A High-Throughput Pipelined Architecture for JPEG XR Encoding,'' In Proc. of 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia2009) , pp. 9-17, October 2009. (Best Paper Award); [126] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 215-218, September 2009.; [127] R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, ``Implementation of Ofdm Baseband Transceiver with Dynamic Spectrum Access for Cognitive Radio Systems,'' In Proc. of 9th International Symposium on Communication and Information Technology (ISCIT2009), pp. 658-663, September 2009.; [128] S. Ninomiya and M. Hashimoto, ``Enhancement of Grid-Based Spatially-Correlated Variability Modeling for Improving Ssta Accuracy,'' In Proceedings of IEEE International SOC Conference (SOCC), pp. 337--340, September 2009.; [129] K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits,'' In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 51--56, August 2009.; [130] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.; [131] Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, and Yukihiro Nakamura, ``Dynamic Rate Control for Media Streaming in High-Speed Mobile Networks,'' In Proc. of IEEE Wireless Communications and Networking Conference (WCNC 2009), April 2009.; [132] M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``An Embedded Sound Localization System for Multiple Sources by Fuzzy Clustering with Spatial Constraints,'' In 2009 International Workshop on Nonlinear Circuits and Signal Processing (NCSP '09), Waikiki, Hawaii, pp. 257-260, March 2009.; [133] S. Watanabe, M. Hashimoto, and T. Sato, ``A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 401--407, March 2009.; [134] Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 236--241, March 2009.; [135] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability,'' In Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.; [136] K. Shinkai and M. Hashimoto, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 79-84, February 2009.; [137] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 266-271, January 2009.; [138] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, ``High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 385--390, January 2009.; [139] M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``A 3D Sound Localization Method for Multiple Sound Sources Based on Fuzzy Clustering,'' In 2008 International Workshop on Smart Info-Media Systems in Bangkok (SISB 2008), pp. 133-138, December 2008.; [140] T. Enami, M. Hashimoto, and T. Sato, ``Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis,'' In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 420-425, November 2008.; [141] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits,'' In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.; [142] Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, and Yukihiro Nakamura, ``An Architecture of Photo Core Transform in HD Photo Coding System for Embedded Systems of Various Bandwidths,'' In Proc. of 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2008), pp. 1592-1595, November 2008.; [143] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 397--400, November 2008.; [144] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, ``On-Chip High Performance Signaling Using Passive Compensation,'' In Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 182-187, October 2008.; [145] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits,'' In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, August 2008.; [146] S. Watanabe, M. Hashimoto, and T. Sato, ``Cascading Dependent Operations for Mitigating Timing Variability,'' In Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008.; [147] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays,'' In In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.; [148] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -,'' In ACM Great Lakes Symposium on VLSI, pp. 387-390, May 2008.; [149] T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' In Proc. ACM International Symposium on Physical Design, pp. 160-167, April 2008.; [150] S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 520-525, March 2008.; [151] H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa, ``Video Image Enhancement Scheme for High Resolution Consumer Devices,'' In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP2008), pp. 639-644, March 2008.; [152] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification,'' In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108, January 2008.; [153] L. Zhang, J. Liu, H. Zhu, C-K Cheng, and M. Hashimoto, ``High Performance Current-Mode Differential Logic,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 720--725, January 2008.; [154] R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, ``VLSI Architecture of H.264 RDO-Based Block Size Decision for 1080 HD,'' In Proc. PCS, November 2007.; [155] R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, ``Implementation of Object Attention Based on Multi-Agent Attractor Selection,'' In Proc. SISB, November 2007.; [156] Yasutake Manabe, Junichi Hara, and Takao Onoye, ``Jpm-Based Differential Image Storage Scheme for Image Revision Management System,'' In IIEEJ Image Electronics and Visual Computing Workshop 2007, November 2007.; [157] K. Takahashi, Y. Nozato, H. Okuhata, and T. Onoye, ``VLSI Architecture for Real-Time Retinex Video Image Enhancement,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 81--86, October 2007.; [158] K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, ``A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 233-237, October 2007.; [159] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 783-786, September 2007.; [160] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' In Proc. IEEE European Solid-State Device Research Conference, pp. 115-118, September 2007.; [161] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, ``Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 869-872, September 2007.; [162] Mohd Nadzrul Bin Mohd Nor, T. Matsumura, and T. Onoye, ``Direction of Arrival Estimation Improvement of Speech on a Two-Microphone Array,'' In IASTED International Conference on Signal and Image Processing, pp. 576-115, August 2007. (Honolulu, Hawaii, USA); [163] K. Shinkai, M. Hashimoto, and T. Onoye, ``Future Prediction of Self-Heating in Short Intra-Block Wires,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 660-665, March 2007.; [164] K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, ``An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control,'' In International Conference on Consumer Electronics Digest of Technical Papers, P1-20, January 2007.; [165] R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, ``VLSI Architecture of H.264 Block Size Decision Based on Rate-Distortion Optimization,'' In Proc. ISPACS, pp. 618--621, December 2006.; [166] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 47-53, November 2006.; [167] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects,'' Proc. IEEE International Conference on Computer Design, pp. 70--75, October 2006.; [168] J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``Probabilistic Pedestrian Tracking Based on a Skeleton Model,'' In Proc. International Conference on Image Processing, pp. 2825--2828, October 2006.; [169] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 721--724, September 2006.; [170] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation,'' In Proc.~IEEE Custom Integrated Circuits Conference, pp. 861--864, September 2006.; [171] T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of Lcd Driver Circuit for Technology Migration,'' In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), vol. 1, p. I25--I28, July 2006.; [172] A. Kosaka and T. Onoye, ``Pipeline Processing of Continuous Speech Recognition Algorithm for Embedded System Implementation,'' In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. Ⅱ, pp. 373--376, July 2006.; [173] F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Signification Extra Bits,'' In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. Ⅲ, pp. 97--100, July 2006.; [174] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227--230, May 2006.; [175] K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Automated Design of Digital Filters for 3-D Sound Localization in Embedded Applications,'' In Proc. International Conf. Audio, Speech, and Signal Processing (ICASSP2006), p. V.349--V.352, May 2006.; [176] H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and Y. Nakamura, ``Efficient Memory Architecture for JPEG2000 Entropy Codec,'' In Proc. International Symposium on Circuits and Systems, pp. 2881--2884, May 2006.; [177] Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``Domain-Specific Reconfigurable Architecture for Media Processing,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2006), pp. 322--327, April 2006.; [178] A. Kotani, Y. Tanemura, Y. Mitsuyama, Y. Asai, Y. Nakamura, and T. Onoye, ``Contour-Based Gravity Center Evaluation of Characters,'' In Proc. EUROMEDIA, pp. 15--20, April 2006.; [179] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 59-64, February 2006.; [180] Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network,'' In International Conference on Consumer Electronics(ICCE2006), digest of technical papers, Las Vegas, Nevada, USA, pp. 391--392, January 2006.; [181] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction,'' In The 3rd International Workshop on Compact Modeling, pp. 51--56, January 2006.; [182] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Interconnect Rl Extraction at a Single Representative Frequency,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 515-520, January 2006.; [183] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, November 2005.; [184] T. Kouno, M. Hashimoto, and H. Onodera, ``Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 453-456, November 2005.; [185] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip High-Throughput Global Signaling,'' In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 79-82, October 2005.; [186] 79-82, ``Estimation of Maximum Oscillation Frequency for Cmos Lcvcos,'' In Estimation of Maximum Oscillation Frequency for CMOS LCVCOs, October 2005.; [187] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Delay Variation Due to Inductive Coupling,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 305--308, September 2005.; [188] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 613-616, September 2005.; [189] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix Lcd,'' In A Design Scheme for Sampling Switch in Active Matrix LCD, August 2005.; [190] Huynh Van Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Real-Time Human Object Extraction for Mobile Terminal,'' In in Proc.The 20th Commemorative International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005), Jeju, Korea, vol. 3, pp. 1015-1016, July 2005.; [191] Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing,'' In Proc. International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC2005), pp. 131--132, July 2005.; [192] T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai, ``3D Sound Movement System for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2005), Kobe, Japan, pp. 5345-5348, May 2005.; [193] R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``High Quality Motion JPEG2000 Coding Scheme Based on the Human Visual System,'' In Proc. IEEE Int’l Symp. Circuits and Systems, pp. 2096--2099, May 2005.; [194] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), May 2005.; [195] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, ``Interconnect Capacitance Extraction for System LCD Circuits,'' In in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005), pp. 160--163, April 2005.; [196] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics,'' In Proceedings of International Meeting for Future of Electron Devices, Kansai, pp. 33-34, April 2005.; [197] A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' In Proceedings of International Symposium on Physical Design (ISPD), pp. 63-69, April 2005.; [198] M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 402-407, March 2005.; [199] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function,'' In in Proc.~International Conference on Consumer Electronics (ICCE2005), digest of technical papers, Las Vegas, Nevada, USA, 7.1-2, January 2005.; [200] T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 723-728, January 2005.; [201] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1098-1101, January 2005.; [202] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Return Path Selection for Loop Rl Extraction,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1078-1081, January 2005.; [203] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, ``On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1074-1077, January 2005.; [204] A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um Cmos Process,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), p. D9-D10, January 2005.; [205] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, 1C-03.3, 2005.; [206] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix LCD,'' In Proceedings of European Conference on Circuit Theory and Design, 3e-212, 2005.; [207] R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``Video Quality Enhancement for Motion JPEG2000 Encoding Based on the Human Visual System,'' In Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 1161--1164, December 2004.; [208] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``VLSI Implementation of 3D Sound Image Movement for Embedded Systems,'' In in Proc. IEEE Region 10 Conference (TENCON) 2004, A--021, November 2004.; [209] K. Tsujino, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, ``Realtime Filter Redesign for Interactive 3-D Sound Systems,'' In Proc. IEEE Region 10 Conference, pp. 124--127, November 2004.; [210] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip Global Signaling,'' In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) , pp. 87-100, November 2004.; [211] M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 814-820, November 2004.; [212] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a 3D Sound Movement System,'' In in Proc. The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2004, pp. 121-125, October 2004.; [213] M. Hashimoto, A. Tsuchiya, and H. Onodera, ``On-Chip Global Signaling by Wave Pipelining,'' In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 311-314, October 2004.; [214] A. Muramatsu, M. Hashimoto, and H. Onodera, ``Lsi Power Network Analysis with On-Chip Wire Inductance,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 55-60, October 2004.; [215] T. Sato, M. Hashimoto, and H. Onodera, ``An Ir-Drop Minimization by Optimizing Number and Location of Power Supply Pads,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 66-72, October 2004.; [216] M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 214-219, October 2004.; [217] T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' In IEEJ International Analog VLSI Workshop, pp. 45-50, October 2004.; [218] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Embedded Architecture of IEEE802.11i Cipher Algorithms,'' In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pp. 241--246, September 2004.; [219] S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa, ``C-Based Hardware Design of IMDCT Accelerator for Ogg Vorbis Decoder,'' In in Proc.12th European Signal Processing Conference (EUSIPCO 2004), pp. 1361--1364, September 2004.; [220] H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, ``Scalable Design Framework for JPEG2000 System Architecture,'' In Proc. Asia-Pacific Computer Systems Architecture Conference, pp. 6--11, September 2004.; [221] J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A Scalable Approach for Estimation of Focus of Expansion,'' In Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pp. 6--11, September 2004.; [222] A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 489-492, September 2004.; [223] A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Optimization of Cmos Current Mode Logic Dividers,'' In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits , pp. 434-435, August 2004.; [224] Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa, ``Architecture of Turbo Decoder for W-CDMA by Configurable Processor,'' In Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4, p. 7, July 2004.; [225] T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, ``Embedded System Implementation of Scalable and Object-Based Video Coding,'' In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.; [226] H. Sugita, Q.-M. Vu, T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura, ``JPEG2000 High-Speed Progressive Decoding Scheme,'' In Proc. IEEE International Symposium on Circuits and Systems, pp. 873--876, May 2004.; [227] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``SoC Design of Ogg Vorbis Decoder Using Embedded Processor,'' In in Proc. 2004 Computing Frontier Conference, pp. 481--487, April 2004.; [228] K. Tsujino, A. Shigiya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, ``An Implementation of Moving 3-D Sound Synthesis System Based on Floating Point Dsp,'' In Proc. IEEE International Symposium on Signal Processing and Information Technology, pp. WA4-8.1-WA4-8.4, December 2003.; [229] K. Tsujino, A. Shigiya, T. Izumi, T. Onoye, Y. Nakamura, and W. Kobayashi, ``A Dsp-Based 3-D Sound Synthesis System for Moving Sound Images,'' In Proc. GAME-ON Conference, pp. 23--25, November 2003.; [230] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Modified Snake: Real-Time Face Object Extraction for Video Phone,'' In in Proc. IEEE International Conference on Image Processing(ICIP2003), Barcelona, Spain, vol. III, pp. 873--876, September 2003.; [231] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``Implementation of W-CDMA Channel Codec by Configurable Processors,'' In Proc. Sixth Baiona Workshop on Signal Processing in Communications, pp. 205--210, September 2003.; [232] Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for TFT Liquid Crystal Displays,'' In in Proc. The European Solid-State Device Research Conference (ESSDERC2003), Estoril, Portugul, pp. 453--456, September 2003.; [233] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Efficient Error Recovery Scheme for MPEG-4 Video Coding,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 2, pp. 1328--1331, July 2003.; [234] Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for On-Chip Interconnects,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and ommunications (ITC-CSCC2003) , Kang-Woo Do, Korea, vol. 3, pp. 1638--1641, July 2003.; [235] A. Kotani, Y. Asai, Y. Nakamura, S. Okada, N. Koyama, K. Yamane, Y.Okano, Y. Mitsuyama, and T. Onoye, ``Visibility Font Technology on High Resolution Color LCD "LCFONT.c",'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003), Kang-Woo Do, Korea, vol. 1, pp. 535--538, July 2003.; [236] S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low Power Ogg Vorbis Decoder by Embedded Processor,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 1, pp. 565--568, July 2003.; [237] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Feature Extraction of Head-Related Transfer Function for 3D Sound Movement,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 1, pp. 685--688, July 2003.; [238] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources,'' In in IEEE 29th International Conference on Consumer Electronics (ICCE2003), digest of technical papers, Los Angeles, Carifornia, USA, pp. 256--257, June 2003.; [239] T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, ``A Novel Signal Processing Scheme for Next Generation GNSS Receiver,'' In in Proc. the 8th ISU International Symposium, Strasbourg, France, May 2003.; [240] M. Hatanaka, T. Masaki, M. Okada, and K. Murakami, ``Implementation of PSK Demodulator for Digital BS/{cs} Broadcasting System,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, vol. II, pp. 764--767, May 2003.; [241] S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Interactive Interface of Realtime 3D Sound Movement for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, vol. II, pp. 520--523, May 2003.; [242] Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Framework for JPEG2000 Encoding System Architecture,'' In Proc. International Symposium on Circuits and Systems, pp. 740--743, May 2003.; [243] T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, ``A Novel Signal Processing Scheme for Next Generation GNSS Receiver and Its VLSI Implementation,'' In in Proc. International Signal Processing Conference , Dallas, no. 357, April 2003.; [244] N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I.Shirakawa, ``Low Cost Approach to Acoustic Field Enhancement for Stereo Headphones,'' In in Proc. Euromedia 2003, Plymouth, United Kingdom, pp. 32--36, April 2003.; [245] S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``A Parasitic Capacitance Modeling Method for Non-Planar Interconnects,'' In in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 294--299, April 2003.; [246] T. Yuasa, A. Tomita, T. Izumi, T. Onoye, and Y. Nakamura, ``An Approach for Circuit Size Reduction by Variable Reordering for Pca-Chip2,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 217--221, April 2003.; [247] T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa, ``Vlsi Architecture for Mpeg-4 Core Profile Codec Core,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 365--371, April 2003.; [248] Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, ``Scalable Design Framework for JPEG2000 Encoder Architecture,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 372--376, April 2003.; [249] T. Yuasa, Y. Soga, T. Izumi, T. Onoye, and Y. Nakamura, ``An Improved Communication Channel in Dynamic Reconfigurable Device for Multimedia Applications,'' In Proc. EUROMEDIA, pp. 152--157, April 2003.; [250] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Realtime Face Object Extraction Algorithm for Video Phone,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), Orchard Road, Singapore, vol. 1, pp. 35--38, December 2002.; [251] Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, ``Implementation of Wireless MPEG2 Transmission System Using IEEE 802.11b PHY,'' In ibid., Orchard Road, Singapore, vol. 1, pp. 39--44, December 2002.; [252] N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acousitic Field Enhancement for Stereo Headphones,'' In ibid., Orchard Road, Singapore, vol. 1, pp. 51--54, December 2002.; [253] S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Multilevel Interconnects,'' In in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002, vol. 1, pp. 59--64, December 2002.; [254] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications,'' In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pp. 20--24, September 2002.; [255] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor,'' In in Proc. 17th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), Phuket, Thailand, pp. 94--97, July 2002.; [256] S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Synthesis of 3D Sound Movement by Embedded DSP,'' In ibid., Phuket, Thailand, pp. 117--120, July 2002.; [257] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Digital Watermark Based Error Detection for MPEG-4 Bitstream Error,'' In ibid., Phuket, Thailand, pp. 152--155, July 2002.; [258] T. Kaya, R. Miyamoto, T. Onoye, and I. Shirakawa, ``Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Processor,'' In ibid., Phuket, Thailand, pp. 216--219, July 2002.; [259] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Hybrid Error Concealment Algorithm for MPEG-4 Videodecoders,'' In ibid., Phuket, Thailand, pp. 611--614, July 2002.; [260] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, O. Tsumori, K. Hanada, T. Chiba, and I. Shirakawa, ``OCEAN: Object Communication Environment for Arbitrary Network,'' In in Proc. IEEE International Conference on Distributed Computing Systems Workshops, pp. 162--166, July 2002.; [261] W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, ```Out-Of-Head' Acoustic Field Enhancement for Stereo Headphones by Embedded DSP,'' In in IEEE 28th International Conference on Consumer Electronics (ICCE2002), digest of technical papers, Cardiff, Wales, pp. 222--223, June 2002.; [262] Y. Ohtani, N. Kawahara, T. Onoye, I. Shirakawa, and T. Chiba, ``MAC LSI Design for Wireless MPEG2 Transmission Over IEEE802.11b PHY,'' In ibid., Los Angeles, pp. 242--243, June 2002.; [263] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``Burst Mode: a New Acceleration Mode for 128-Bit Block Ciphers,'' In in Proc. IEEE 24th Custom Integrated Circuits Conference (CICC2002), Orland, Florida, pp. 151--154, May 2002.; [264] Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Digital Matched Filter and Prime Interleaver for W-CDMA,'' In Proc. IEEE International Symposium on Circuits and Systems (ISCAS2002), Phoenix, Arizona, vol. III, pp. 269--272, May 2002.; [265] Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers,'' In ibid., Phoenix, Arizona, vol. II, pp. 344--347, May 2002.; [266] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Power Estimation at Architecture Level for Embedded Systems,'' In ibid., Scottsdale, Arizona, vol. II, pp. 476--479, May 2002.; [267] Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, and T. Chiba, ``Error Correction Block Based ARQ Protocol for Wireless Digital Video Transmission,'' In ibid., Phoenix, Arizona, vol. I, pp. 605--608, May 2002.; [268] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``A Java Accelerator for High Performance Embedded Systems,'' In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.; [269] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Synthesis Algorithm for Monaural Sound Source,'' In in Proc. EUROMEDIA 2002, Modena, Italy, pp. 123--127, April 2002.; [270] M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, ``High Performance Java Hardware Engine and Software Kernel for Embedded Systems,'' In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pp. 365--369, December 2001.; [271] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``An Architecture Level Power Estimation Method for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 78--85, October 2001.; [272] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``System Performance Evaluation of High-Speed Burst Mode for 128-Bit Block Ciphers,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 332--339, October 2001.; [273] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``High Performance Java Execution for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 346--350, October 2001.; [274] M. Ise, Y. Uchida, T. Onoye, and I. Shirakawa, ``System-On-A-Chip Architecture for W-CDMA Baseband Modem LSI,'' In in Proc. The 4th International Conference on ASIC (ASICON 2001), Shanghai, pp. 364--369, October 2001.; [275] M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa, ``Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 589--592, September 2001.; [276] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementaion of 3D Sound Localization Algorithm for Monaural Sound Source,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 1061--1064, September 2001.; [277] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Low Computational 3D Sound Localization Algorithm,'' In in Proc. 200l IEEE Workshop on Signal Processing Systems, Design and Implementation(SIPS 2001), Antwerp, Belgium, pp. 109--116, September 2001.; [278] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers,'' In in Proc. 14th Annual IEEE International ASIC/SoC Conference (ASIC/SoC2001), Washington, D.C., pp. W.1.1.1--W.1.1.5, September 2001.; [279] H. Okada, H. S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Detection Based on Check Marker Embedding for MPEG-4 Video Coding,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 96--99, July 2001.; [280] H. S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Concealment Algorithm by Motion Estimation Method for MPEG-4 Video Decoder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 104--107, July 2001.; [281] T. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Low Power Architecture for H.263 Version2 Codec,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 620--623, July 2001.; [282] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Localization Algorithm,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 1140--1143, July 2001.; [283] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization for Monaural Sound Source,'' In in Proc. World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001), Orlando, Florida, USA, pp. 173--177, July 2001.; [284] M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, ``Evaluation of Processor Code Efficiency for Embedded Systems,'' In in Proc. ACM 15th International Conference on Supercomputing, Sorrento, Italy, pp. 229--235, June 2001.; [285] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, vol. IV, pp. 734--737, May 2001.; [286] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A High Performance Burst Mode Approach for 128-Bit Block Ciphers,'' In in Proc. EUROMEDIA2001, Valencia, Spain, pp. 146--150, April 2001.; [287] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A Dynamically Reconfigurable Hardware-Based Cipher Chip,'' In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 11--12, January 2001.; [288] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``Realtime Wavelet Video Coder Based on Reduced Memory Accessing,'' In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 15--16, January 2001.; [289] S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Portable MPEG-4 Audio Decoder,'' In in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA, pp. 80--84, September 2000.; [290] Y. Dong, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder,'' In in Proc. International Conference on Image Processing (ICIP 2000), vol. III, pp. 126--129, September 2000.; [291] K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A Shingle Chip Automotive Control LSI Using SOI BiCDMOS,'' In in Proc. of 2000 International Conference on Solid State Device and Materials, pp. 486-487, August 2000.; [292] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization,'' In in Proc. ITC-CSCC 2000, Pusan, Korea, pp. 253--256, July 2000.; [293] W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' In in Proc. ITC-CSCC 2000, Pusan, Korea, pp. 264--267, July 2000.; [294] R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa, ``Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec,'' In in Proc. ITC-CSCC 2000, Pusan, Korea, pp. 811--814, July 2000.; [295] T. Watanabe and N. Ishiura, ``Minimization of Spill Code Insertion by Register Constraint Analysis for Code Generation for Application Specific DSPs,'' In in Proc. ITC-CSCC 2000, Pusan, Korea, pp. 953--956, July 2000.; [296] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Symposium on VLSI Circuits Digest of Technical Papers, Hawaii, USA, pp. 204--205, June 2000.; [297] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``Chameleon: a Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pp. 90--94, May 2000.; [298] M. Hatanaka, T. Masaki, and K. Murakami, ``An Efficient Network Architecture for AAL Type2 and Its VLSI Implementation,'' In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pp. 123--125, May 2000.; [299] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a Realtime Wavelet Video Coder,'' In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pp. 543--546, May 2000.; [300] N. Ishiura, T. Watanabe, and M. Yamaguchi, ``A Code Generation Method for Datapath Oriented Application Specific Processor Design,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pp. 71--78, April 2000.; [301] M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, ``Thread Partitioning Method for Hardware Compiler Bach,'' In in Proc.\ Asia and South Pacific Design Automation Conference (ASP-DAC 2000), pp. 303--308, January 2000.; [302] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic,'' In in Proc. ASP-DAC2000, pp. 529--532, January 2000.; [303] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Video Coding Algorithm Based on Modified Discrete Wavelet Transform,'' In in Proc. NOLTA'99, vol. I, pp. 251--254, November 1999.; [304] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Architecture of Embedded Zerotree Wavelet Based Real-Time Video Coder,'' In in Proc. 12th IEEE ASIC/SOC Conference, pp. 137-141, October 1999.; [305] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Embedded Zerotree Wavelet Based Algorithm for Video Compression,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp.II-1343--1346, September 1999.; [306] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 872--875, September 1999.; [307] M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa, ``High-Speed Implementation of JBIG Arithmetic Coder,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 1291--1294, September 1999.; [308] N. Ishiura and M. Yamaguchi, ``Operation Binding for Retargetable Compilers Minimizing Clock Cycles,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 705--708, July 1999.; [309] B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 561--564, July 1999.; [310] M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa, ``Pipelined Implementation of JBIG Arithmetic Coder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 470--473, July 1999.; [311] M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, ``Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, vol. IV, pp. 572--575, June 1999.; [312] H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, ``Hybrid Media-Processor Core for Natural and Synthetic Video Decoding,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, vol. IV, pp. 275--278, June 1999.; [313] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``Low-Power Architecture of H.324 Codec Dedicated to Mobile Computing,'' In in Proc. EUROMEDIA'99 , Munich, Germany, pp. 145--149, April 1999.; [314] K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, ``Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware,'' In in Proc. IEEE Internatinal Solid-State Circuits Conference, pp. 106--107, February 1999.; [315] H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, ``Hybrid VLSI Architecture for Motion Compensation and Texture Mapping,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 383--386, November 1998.; [316] J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, ``Structual Objeco-Oriented Video Segmentation and Representation Algorithm,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 78--82, November 1998.; [317] H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura, ``Matrix-Vector Multiplier Module for Natural/Synthetic Hybrid Video Coding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 631--634, November 1998.; [318] N. Ishiura, M. Yamaguchi, and T. Kambe, ``A Graph-Based Algorithm of Operation Binding for Compilers Targeting Heterogeneous Datapath,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 395--398, November 1998.; [319] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Implementation by a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 235--240, October 1998.; [320] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Delay and Power Simulation for a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. European Simulation Symposium, pp. 339--343, October 1998.; [321] J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, ``Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding,'' In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pp. 141--151, September 1998.; [322] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System Constructed of SAW-Based Receiver/Transmitter and Its Applications to Medical Cares,'' In in Proc. IEEE Radio & Wireless Conf., pp. 47--50, August 1998.; [323] Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Function Module for Texture Mapping and Motion Compensation,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 179--182, July 1998.; [324] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Implementation of DWT and EZW Cores for a Bitrate Scalable Video Coder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 221--224, July 1998.; [325] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System by Means of SAW-Based Transmitter/Receiver and Its Applications to Medical Cares,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 299--302, July 1998.; [326] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``Matrix-Vector Multiplier for Natural/Synthetic Hybrid Video Coding,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1269--1272, July 1998.; [327] D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, ``VLSI Implementation of a Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1383--1386, July 1998.; [328] N. Ishiura, M. Yamaguchi, and N. Nitta, ``Field Partitioning Algorithms for Compression of Instruction Codes of Application Specific VLIW Processors,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1387--1390, July 1998.; [329] M. Yamaguchi, N. Ishiura, and T. Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal Datapath Architectures,'' In in Proc. International Symposium on Circuits and Systems, WPA4-4, June 1998.; [330] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data Systems Constructed of SAW-Divices and Its Applications to Medical Cares,'' In in Proc. Analog VLSI WS, pp. 39--44, June 1998.; [331] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``Implementation of H.324 Audiovisual Codec for Mobile Computing,'' In in Proc.\ IEEE Custom Integrated Circuits Conference, pp. 193--196, May 1998.; [332] H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``A Low Power DSP Core Architecture for Low Bitrate Speech Codec,'' In in Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal Processing, pp. 3121--3124, May 1998.; [333] M. Yamaguchi, N. Ishiura, and T. Kambe, ``Binding and Scheduling Algorithms for Highly Retargetable Compilation,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 93-98, February 1998.; [334] T. Onoye, G. Fujita, H. Okuhata, M. H. Miki, and I. Shirakawa, ``Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 589-594, February 1998.; [335] N. Ishiura and M. Yamaguchi, ``Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning,'' In in Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), pp. 105-109, December 1997.; [336] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Performance Evaluation of Shared VCI Cell for Multimedia ATM Network,'' In in Proc. International Seminar on Teletraffic and Network, pp. 482-485, November 1997.; [337] H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi, ``A Unified Media-Processor Architecure for Video Coding and Computer Graphics,'' In in Proc. International Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional Imaging, pp. 253-256, September 1997.; [338] M. H. Miki, G.Fujita, T. Onoye, and I. Sirakawa, ``Low-Power H.263 Video CoDec Dedicated to Mobile Computing,'' In in Proc. International Symposium on Low Power Electronics and Design, pp. 80-83, August 1997.; [339] H. Uno, K. Kumatani, H. Okuhata, T. Chiba, and I. Shirakawa, ``Low Power Architecture for High Speed Infrared Wireless Communication System,'' In in Proc.International Symposium on Low Power Electronics and Design, pp. 255-258, August 1997.; [340] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``An Object Code Compression Approach to Embedded Processors,'' In in Proc. International Symposium on Low Power Electronics and Design, pp. 265-268, August 1997.; [341] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Fellow Cell Switching for Voice Communication on Multimedia ATM Network and Its VLSI Implementation,'' In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pp. 1219-1222, July 1997.; [342] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``Media-Processor Architecture Unified for Video Coding and 3D Graphics,'' In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pp. 1223-1226, July 1997.; [343] G. Fujita, T. Onoye, and I. Sirakawa, ``A New Motion Estimation Core Dedicated to H.263 VideoCoding,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1161-1164, June 1997.; [344] M.Yamaguchi, T. Nakaoka, A. Yamada, and T. Kambe, ``An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1584-1587, June 1997.; [345] I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimun Cost Flow Algofithm for VLSI Layout Compaction,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1672-1675, June 1997.; [346] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, ``Multimedia ATM Network Using Shared VCI Cell and VLSI Implementation of Rerouting Node,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 2793-2796, June 1997.; [347] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication,'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 229-232, May 1997.; [348] H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Link Dedicated to Mobile Computing,'' In in Proc. IEEE International Performance, Computing, and Communications Conference, pp. 463-467, February 1997.; [349] M. Yamaguchi, A. Yamada, T. Nakaoka, and T. Kambe, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pp. 503-508, January 1997.; [350] S. Morikawa, K. Okada, S. Takeuchi, and I. Shirakawa, ``A High Performance FIR Filter Dedicated to Digital Video Transmission,'' In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pp. 77-82, January 1997.; [351] H. Kondo, A. Sugiyama, and M. E. Cannon, ``Precise Carrier Phase GPS and Its Application to Real-Time Landslide Detection,'' In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pp. 906-911, November 1996.; [352] G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura, ``Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pp. 949-954, November 1996.; [353] H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Communication System Dedicated to Mobile Computing,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 334-337, November 1996.; [354] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 480-483, November 1996.; [355] Y. Konno, K. Nakamura, T. Bitoh, K. Saga, and S. Yano, ``A Consistent Scan Design System for Large-Scale ASICs,'' In in Proc. Fifth Asian Test Symposium, pp. 82-87, November 1996.; [356] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low-Power Consumption Architecture for Embedded Processor,'' In in Proc. 2nd International Conference on ASIC, pp. 77-80, October 1996.; [357] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``Implementation of Very Low Bitrate Video Encoder Core,'' In in Proc. 2nd International Conference on ASIC, pp. 131-134, October 1996.; [358] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura, ``A Single Chip Motion Estimator Dedicated to MPEG2 MP@{hl},'' In in Proc. European Signal Processing Conference, pp. 1479-1482, September 1996.; [359] G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa, ``Single Chip MPEG2 MP@{ml} Motion Estimator,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 286-289, July 1996.; [360] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Architecture for Very Low Bitrate Video Encoder Core,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 294-297, July 1996.; [361] S. Nakamura, N. Ishiura, T. Yamamoto, and I. Shirakawa, ``High-Level Synthesis System for Behavioral Descriptions with Conditional Branches,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 935-938, July 1996.; [362] Y. Shigehiro, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm and Its Application to VLSI Layout Compaction,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 951-954, July 1996.; [363] H. Uno, K. Kumatani, H. Okuhata, T. Masaki, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Communication Link for Mobile Computing,'' In in Proc. Workshop on Multi-Dimensional Mobile Communications (MDMC '96), pp. 267-271, July 1996.; [364] N. Shimizu, Y. Mizuta, H. Kondo, and H. Ono, ``A New GPS Real-Time Monitoring System for Deformation Measurements and Its Application,'' In in Proc. 8th FIG Int. Symp. Deformation Measurements, Hong Kong, S1.5, pp. 47-54, June 1996.; [365] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 351-354, May 1996.; [366] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``A VLSI Architecture of MPEG2 MP@{hl} Motion Estimator,'' In in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 664-667, May 1996.; [367] K. Itoh, Y. Shigehiro, I. Shirakawa, and K. Matsumura, ``An Approach for Multi-Layer Gridless Routing,'' In in Proc. Printed Circuit World Convention VII, pp.P2-1-P2-7, May 1996.; [368] N. Shimizu, K. Nakagawa, and H. Kondo, ``Displacement Monitoring by Using Global Positioning System,'' In in Proc. 4th Int. Symp. Field Measurements in Geomechanics, %Bergamo, Italy, pp. 555-562, April 1996.; [369] M. Furuie, T. Onoye, S. Tsukiyama, and Isao Shirakawa, ``Two-Dimensional Array Layout for Low Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Conference on Electronics Packaging(2001 ICEP), Tokyo, April, 2001., pp. 417--421, .
Domestic Conference: [1] 岩瀬大輝, 伊藤雄一, 秦秀彦, 山下真由, 尾上孝雄, ``アクティブ音響センシングによる日常物体識別と位置推定,'' インタラクション2018論文集, pp. 62-71, February 2018.; [2] 井上佑貴, 伊藤雄一, 尾上孝雄, ``TuVe: チューブを用いたディスプレイ,'' インタラクション2018, 2018.; [3] 秋原優樹, 廣瀬哲也, 田中勇気, 黒木修隆, 沼昌宏, 橋本昌宜, ``小型センサデバイスに向けた無線給電システムの設計,'' 回路とシステムワークショップ, pp. 258--263, April 2015.; [4] 中島康祐, 伊藤雄一, Simon Voelker, Christian Thoresen, Kjell Ivar Øvergård, Jan Borchers, ``PUCs: 静電容量方式マルチタッチパネルにおけるユーザの接触を必要としないウィジェット検出手法,'' インタラクション2014論文集, March 2014.; [5] 中島康祐, 伊藤雄一, 遠藤隆介, 岸野文郎, ``複合商業施設での複数人によるタイムスロット考慮型プランニングを実現するデジタルサイネージシステム,'' インタラクション2014論文集, March 2014.; [6] 中島康祐, 伊藤雄一, 林勇介, 池田和章, 藤田和之, 尾上孝雄, ``Emoballoon: ソーシャルタッチインタラクションのための柔らかな風船型インタフェース,'' インタラクション2013論文集, pp. 95-102, March 2013.; [7] 安藤正宏, 細井俊輝, 中島康祐, 伊藤雄一, 北村喜文, 尾上孝雄, ``ブロック型デバイスのための赤外線を用いた積み重ね形状認識におけるブロック間距離の影響に関する検討,'' 日本バーチャルリアリティ学会研究報告, vol. 18, no. CS-4, pp. 11-14, 2013.; [8] 小島康介, 橋本亮司, 藤田玄, ``H.264 向け量子化パラメータを考慮した動きベクトル検出手法の一検討,'' 第22回回路とシステム軽井沢ワークショップ , pp. 142-147, April 2009.
Workshop: [1] Mayu Yamashita, Yuichi Itoh, Kazuki Takashima, Takao Onoye, ``Estimation of Understanding Situation of Learner by Pen Gripping Force,'' 電子情報通信学会技術研究報告, vol. 117, no. 509, pp. 47-52, March 2018.; [2] 白井僚, 河野仁, 廣瀬哲也, 橋本昌宜, ``近傍界磁界通信・電界測距共用mm^3級アンテナの実装と評価,'' 電子情報通信学会技術研究報告, vol. Vol. 117, no. No. 343, pp. 101--105, December 2017.; [3] 白井僚, 廣瀬哲也, 橋本昌宜, ``IoTノード向けアンテナ組込型小体積高効率トランスミッタの開発,'' 電子情報通信学会技術研究報告, vol. Vol. 117, no. No. 343, pp. 159--163, December 2017.; [4] 岩瀬大輝, 伊藤雄一, 秦秀彦, 山下真由, 尾上孝雄, ``アクティブ音響センシングを用いた物体識別と位置推定,'' 電子情報通信学会技術研究報告, vol. 117, no. 73, pp. 135-140, June 2017.; [5] 白井僚，廣瀬哲也，橋本昌宜, ``超小型IoTノード向けアンテナ組み込み型OOKトランスミッタの実装と評価,'' 第45回アナログRF研究会, p. 2, March 2017.; [6] Masaki Masuyama, Yuichi Itoh, Kosuke Fukushima, Takao Onoye, ``Chair Caster Device to Get the Center of Pressure and Weight of a Sitting Person,'' ヒューマンコミュニケーション基礎研究会（HCS）, vol. 116, no. 524, pp. 95-100, March 2017.; [7] Mayu Yamashita, Yuichi Itoh, Kazuki Takashima, Takao Onoye, ``A Study on Relationship between Learner's Confidence and Writing Behavior,'' ヒューマンインタフェース学会研究会研究報告集, vol. 19, no. 7, pp. 71-76, 2017.; [8] 深町太一, 伊藤雄一, 尾上孝雄, ``光信号を用いたアクチュエータ群制御システムの検討と評価,'' 日本バーチャルリアリティ学会研究報告, vol. 21, no. CS-4, pp. 17-20, December 2016.; [9] K. Fujiwara, Y. Itoh, T. Tsuzuki, K. Takashima, T. Onoye, ``Estimating Ensembility among Players Using Their Body Sway and the Evaluation Toward Music Performance,'' HCGシンポジウム2016論文集, pp. 186-189, December 2016.; [10] S. Shoda, L. JIN, M. Hatanaka, T. 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Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Technical Report, CAS2008-14, VLD2008-27, SIP2008-48(2008-6), pp. 75-79, June 2008.; [82] 服部幸市, 筒井弘, 越智裕之, 中村行宏, ``バス帯域を考慮した HD Photo における Photo Core Transform のアーキテクチャ,'' IEICE Technical Report, SIS2008-21, vol. 108, no. 85, pp. 39-44, June 2008.; [83] Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Superposition Effect Validation of Inductive Coupling Noise Based on Measurement of Interconnect Delay Variation,'' , 信学技報, VLD2007-153, March 2008.; [84] Y. Ogasahara, M. Hashimoto, T. Onoye, ``All Digital Gated Oscillator for Dynamic Supply Noise Measurement,'' IEICE Technical Report, CPM2007-131, ICD2007-142, pp. 17-22, January 2008.; [85] H. Kato, A. Yamada, T. Onoye, ``An Image Compression Method for Frame Memory Reduction,'' 電子情報通信学会 CAS信学技報, vol. 107, no. 476, pp. 31-36, January 2008.; [86] Shinyu Ninomiya, Masanori Hashimoto, ``A Study of Grid-Based Modeling of Spatially Correlated Manufacturing Variability for SSTA,'' IEICE Technical Report, VLD2007-91, DC2007-46, vol. 107, no. 336, pp. 13-17, November 2007.; [87] Ryoji HASHITMO, Kimiya KATO, Makoto SAITSUJI, Teruhito TANAKA, Hirokazu UETSU, Gen FUJITA, Takao ONOYE, ``Vlsi Architecture of H.264 Multi-Symbol Entropy Decoder for 1080hd,'' 第21回ディジタル信号処理シンポジウム, November 2007.; [88] Kimiya Kato, Ryoji Hashimoto, Gen Fujita, Takao Onoye, ``Vlsi Architecture of Multi-Symbol Cabac Decoder for H.264/Avc High Profile,'' 信学技報, SIP2007-121, ICD2007-110, IE2007-80, pp. 65-70, October 2007.; [89] 橋本昌宜, ``製造・環境ばらつきを考慮したタイミング検証技術,'' 信学技報, VLD2007-65, pp. 21-24, October 2007.; [90] S. Abe, M. Hashimoto, T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' 情報処理学会DAシンポジウム, pp. 133-138, August 2007.; [91] Hiroshi Tsutsui, Norimasa Fujita, Takao Onoye, Yukihiro Nakamura, ``A Multi-Symbol Arithmetic Decoder for JPEG2000,'' IEICE Technical Report, SIS2007-3, vol. 107, no. 93, pp. 13--18, June 2007.; [92] K. Shinkai, M. Hashimoto, T. Onoye, ``Self-Heating in Short Intra-Block Wires,'' Proc. The 20th Workshop on Circuits and Systems in Karuizawa, pp. 7-12, April 2007.; [93] T. Enami, S. Ninomiya, M. Hashimoto, ``Statistical Timing Analysis Considering Spatially Correlated Dynamic Power Supply Noise,'' Proc. The 20th Workshop on Circuits and Systems in Karuizawa, pp. 667-672, April 2007.; [94] 橋本昌宜, ``製造・環境ばらつきと動的性能補償を考慮したタイミング検証に向けて,'' 第20回回路とシステム(軽井沢)ワークショップ, pp. 661-666, April 2007.; [95] Y. Ogasahara, M. Hashimoto, T. Onoye, ``Measurement of Delay Variation Due to Inductive Coupling Noise in 90nm Global Interconnects,'' IEICE Technical Report, CPM2006-131, ICD2006-173, pp. 13--18, January 2007.; [96] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye, ``Measurement of Delay Degradation Due to Power Supply Noise and Delay Variation Estimation with Full-Chip Simulation,'' IEICE Technical Report, CPM2006-132, ICD2006-174, pp. 19--23, January 2007.; [97] T. Matsumura , A. Yoshida, N. Iwanaga, W. Kobayashi, T. Onoye, ``An Approach to Perceptual Improvement of 3d Sound Movement by Reproduction of Head-Related Transfer Function,'' Trans. Tech. Comm. Psychol. Physio. Acoust, The Acoustical Society of Japan, vol. 36, no.9, H--2006--135, December 2006.; [98] A. Yoshida, T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, ``A Method for Improvement of Sound Localization in the Proximal Region,'' Trans. Tech. Comm. Psychol. Physio. Acoust., The Acoustical Society of Japan,, H-2006-134, December 2006.; [99] R. Hashimoto, G. Fujta, T. Onoye, ``Dynamic Time Allocation Scheme in H.264 Encoding,'' IEICE The 21th SIP Symposium, D8-1, November 2006.; [100] Y.Tanemura, A.Kotani, S.Yamazaki, Y.Mitsuyama, T.Onoye, ``Estimation Method of Typographic Color Considering Visual Features,'' IEICE Technical Report SIS2006-70, vol. 106, no. 374, pp. 69--74, November 2006.; [101] Y. NOZATO, K. TAKAHASHI, H. OKUHATA, T. ONOYE, ``Architecture for Lightness Presumption in Real-Time Video Image Enhancement,'' IEICE The 21th SIP Symposium, D8-3, November 2006.; [102] Jangsombatsiri Siriporn, 橋本昌宜, 尾上孝雄, ``シャントコンダクタンスを挿入したオンチップ伝送線路特性評価,'' 第十回シリコンアナログRF研究会, November 2006.; [103] T. Enami, M. Hashimoto, T. Onoye, ``Statistical Modeling of Power/Ground Voltage Variation by Principal,'' 情報処理学会DAシンポジウム, pp. 205--210, July 2006.; [104] K. Takahashi, Y. Nozato, H. Okuhata, T. Onoye, ``Reduced-Complexity Variational Retinex for Video Image Enhancement,'' IEICE Technical Report, SIS2006-3, pp. 13--18, June 2006.; [105] G. Fujita, K. Ohkubo, K. Joko, M. Saitsuji, T. Onoye, ``Efficient Vlsi Architecture for H.264 Cabac,'' IEICE Technical Report, SIS2006-34, pp. 19--23, June 2006.; [106] K. Shinkai, M. Hashimoto, A. Kurokawa, T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' Proc. The 19th Workshop on Circuits and Systems in Karuizawa, pp. 559-564, April 2006.; [107] Y. Ogasahara, M. Hashimoto, T. Onoye, ``Quantitative Prediction of Capacitive and Inductive Crosstalk Noise in LSI Interconnects,'' IEICE The 19th Workshop on Circuits and Systems in Karuizawa, pp. 5--10, April 2006.; [108] M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, I. Shirakawa, ``Wireless Network Protocol for Home Network Based on IEEE 802.15.4,'' IEICE Technical Report, CAS2005-99, pp. 19--24, March 2006.; [109] K. Watanabe, M. Ise, G. Fujita, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, I. Shirakawa, ``Improvement of Power Consumption and Response Time in Wireless Home Network,'' IEICE Technical Report, CAS2005-100, pp. 25--30, March 2006.; [110] T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, I. Shirakawa, ``Transistor Sizing for LCD Driver Circuit under Constraint of Charged Pixel Voltage,'' Proc. Technical Report of IEICE, VLD2005-131, pp. 55--60, March 2006.; [111] T. Imafuku, N. Iwanaga, T. Matsumura, W. Kobayashi, T. Onoye, ``An Approach to 3D Sound Movement for Multiple Sound Sources,'' IEICE Technical Report, SP2005-131, pp. 47-52, March 2006.; [112] G. Fujita, T. Onoye, I. Shirakawa, ``Vlsi Implementation of High Accuracy Motion Estimation Core for Mpeg-4,'' IEICE Trans. Fundamentals, vol. J88-A, no. 11, pp. 1282--1291, November 2005.; [113] A. Kotani, Y. Tanemura, Y. Asai, Y. Nakamura, M. OTSUKA, Y. MITSUYAMA, T. Onoye, ``Evaluation Method of Center of Gravity on FONT and Its Application to Readability Assessment,'' IEICE Technical Report SIS2005-23, pp. 1--6, September 2005.; [114] Y. Ogasahara, M. Hashimoto, T. Onoye, ``Measurement and Evaluation of Delay Variation Due to Inductive and Capacitive Coupling Noise,'' IEICE Technical Report, SDM2005-135, ICD2005-74, pp. 43--48, August 2005.; [115] A. Yoshida, T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, ``Feature Analysis of Head-Related Transfer Function for Sound Localization of Nearby Sources,'' IEICE Technical Report EA2005-39, pp. 29--34, August 2005.; [116] Y. Nozato, H. Okuhata, T. Onoye, I. Shirakawa, ``Comparison of Retinex Models for Hardware Imprementation,'' IEICE Technical Report SIS2005-16, pp. 19--24, June 2005.; [117] G. Fujita, T. Imanaka, Huynh Van Nhat, T. Onoye, I. Shirakawa, ``Real-Time Human Object Extraction Method Based on Color Space Segmentation for Mobile Systems,'' in Proc.The 18th Workshop on Circuits and Systems in Karuizawa, pp. 431--436, April 2005.; [118] ワットカナッド・ウィラポーン, 木村基, 藤田玄, 尾上孝雄, 白川功, ``動画像マルチデコーダ用動き補償機構のVLSIアーキテクチャ,'' Proc. Technical Report of IEICE, SIS2004-62, pp. 37--43, March 2005.; [119] 郭朝暉, 西川裕規, 大巻ロベルト裕治, 尾上孝雄, 白川功, ``Motion JPEG2000 における誤り訂正符号の割当て手法,'' 信学技報, CAS2004-67, pp. 1--6, January 2005.; [120] 盧承烈, 小笠原泰弘, 伊勢正尚, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``ユニバーサルプラグアンドプレイ技術を用いたホームネットワーク一構成方式,'' 信学技報, CAS2004-68, pp. 7--12, January 2005.; [121] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa, ``Interconnect Capacitance Extraction for System LCD Circuits,'' Proc. Technical Report of IEICE, VLD2004-64, pp. 19--24, December 2004.; [122] A. Kotani, Y Asai, Y Nakamura, M Ootuka, Y. Mitsuyama, T. Onoe, ``Contour-Based Evaluation Method of Center of Gravity on "LCFONT",'' Proc. Technical Report of IPSJ, 2004-HI-111, pp. 63--70, November 2004.; [123] 木村基, 密山幸男, 尾上孝雄, 白川功, ``組込みシステム向け IEEE802.11i 暗号処理回路の実装,'' 信学技報, ICD2004-129, pp. 49--54, October 2004.; [124] 今井林太郎, 密山幸男, 尾上孝雄, 白川功, ``メディア処理向けリコンフィギュラブルアーキテクチャに関する一検討,'' 電子情報通信学会第4回リコンフィギャラブルシステム研究会, pp. 33--40, September 2004.; [125] M. Kimura, Y, Mitsuyama, T. Onoye, I. Shirakawa, ``Embedded Implementation of IEEE802.1i Cipher Algorithms,'' Proc. Technical Report of IEICE, ICD2004-129, pp. 217--222, April 2004.; [126] Y. Nakagawa, N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, I. Shirakawa, ``Binaural Sound Reproduction Based on Frequency Characteristic Elimination Through Stereo Speakers,'' Trans. Tech. Comm. Psychol. Physiol. Acoust.,The Acoustical Society of Japan, pp. 17--22, January 2004.; [127] Y. Uchida, S. Tani, S. Tsukiyama, I. Shirakawa, ``Parasitic Capacitance Modeling for On-Chip Interconnects,'' Technical Report of IEICE, NLP2003-21, pp. 7--12, June 2003.; [128] N. Iwanaga, N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa, `` `Out-Of-Head' Acoustic Field Enhancement with Stereo Headphone for Embedded System and Its Implementation,'' Proc. IEICE the 17th Digital Signal Processing Symposium, B2-4, November 2002.; [129] N. Kawahara, Y. Ohtani, T. Onoye, I. Shirakawa, ``A Design of Video Transmission System Using IEEE802.11b PHY,'' ibid, B6-1, September 2002.; [130] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, I. Shirakawa, ``VLSI Implementation of Ogg Vorbis Audio Decoder with Embedded Processor and Specific Hardware,'' Technical Report of IEICE, SDM2002-159, ICD2002-70, pp. 37--42, August 2002.; [131] S. Tani, Y. Uchida, S. Tsukiyama , I. Shirakawa, ``A Parasitic Capacitance Modeling Method for Multilevel Interconnects,'' Technical Report of IEICE, DSP2002-83, pp. 7--12, June 2002.; [132] T. Okada, T. Uchida, T. Onoye, I. Shirakawa, ``Architecture of Pseudo Random Noise Code Generator for Next-Generation GNSS Receiver,'' Technical Report of IEICE, DSP2002-69, pp. 19--24, June 2002.; [133] H. Song, A. Shiitev, H. Okada, G. Fujita, T. Onoye, I. Shirakawa, ``Error Concealment Algorithm in MPEG-4 Video Coding,'' IEICE The 15th Workshop on Circuits and Systems in Karuizawa, pp. 95--100, April 2002.; [134] K. Nakagawa, M. Kawakita, K. Sato, K. Hanada, T. Chiba, I. Shirakawa, ``Adaptive Object Sharing Scheme for Heterogeneous Environment,'' IEICE The 15th Workshop on Circuits and Systems in Karuizawa, pp. 161--166, April 2002.; [135] H. Mizuno, H. Kobayashi, T. Onoye, I. Shirakawa, ``Power Estimation at Architecture Level for Embedded System,'' IEICE The 15th Workshop on Circuits and Systems in Karuizawa, pp. 435--440, April 2002.; [136] T. Nakagawa, S. Hamanaka, X. Y. He, G. Fujita, I. Shirakawa, ``VLSI Architecture for MPEG-4 Core Profile Video Codec,'' TECHNICAL REPORT OF IEICE, VLD2001-136, pp. 31--38, January 2002.; [137] M. Kimura, M. H. Miki, T. Onoye, I. Shirakawa, ``Implementation of Java Execution Environment for Embedded Systems,'' TECHNICAL REPORT OF IEICE, VLD2001-137, pp. 39--44, January 2002.; [138] Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, ``Error Correction Block Based ARQ Method for Video Transmission System,'' DSP Symposium, pp. 711--717, November 2001.; [139] Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, ``Design of a Wireless Digital Video Transmission System with Data Frame Selective Repeat Hybrid ARQ Protocol,'' TECHNICAL REPORT OF IEICE, CAS2001-93, pp. 25--30, November 2001.; [140] K. Nakagawa, K. Sato, O. Tsumori, K. Hanada, I. Shirakawa, ``Object Communication Environment for Arbitrary Network (OCEAN),'' DPS Workshop, pp. 19--24, September 2001.; [141] H. S. Song, A. E. Shiitev, H. Okada, G. Fujita, T. Onoye, I. Shirakawa, ``Error Concealment Algorithm and Architecture for MPEG-4 Video Transmission,'' TECHNICAL REPORT OF IEICE, CAS2001-10, pp. 71--77, June 2001.; [142] Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, ``VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers,'' TECHNICAL REPORT OF IEICE, CAS2001-41, pp. 89--94, June 2001.; [143] N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Localization Algorithm and Its Evaluation,'' TECHNICAL REPORT OF IEICE, CAS2001-50, pp. 147--154, June 2001.; [144] G. Fujita, M. Tarui, K. Hontani, H. Okuhata, I. Shirakawa, ``Realtime Extraction Algorithm Dedicated to Face Objects,'' TECHNICAL REPORT OF IEICE, DSP2001-31, pp. 87--92, June 2001.; [145] M. H. Miki, M. Sakamoto, Y. Takeuchi, T. Yoshida, I. Shirakawa, ``Evaluation of Processor Code Efficiency for Embedded Systems,'' IEICE The 14th Karuizawa Workshop on Circuits and Systems, pp. 113--118, April 2001.; [146] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A New Approach for 128-Bit Block Ciphers,'' In IEICE The 14th Karuizawa Workshop on Circuits and Systems, pp. 231--236, April 2001.; [147] T. Song, H. S. Song, G. Fujita, T. Onoye, I. Shirakawa, ``VLSI Design of H.263 Version2 Codec Core,'' IEICE The 14th Karuizawa Workshop on Circuits and Systems, pp. 561--566, April 2001.; [148] N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa, ``Embedded DSP Implementation of Realtime 3D Sound Localization Algorithm for Monaural Sound Source,'' IEICE the 15th DIGITAL SIGNAL PROCESSING SYMPOSIUM. C6-2, pp. 599--604, November 2000.; [149] T. Watanabe, N. Ishiura, ``Datapath Oriented Codesign Method of Application Specific DSPs by Retargetable Compiler,'' TECHNICAL REPORT OF IEICE, VLD2000-89, pp. 119--124, November 2000.; [150] H. S. Song, T. Song, H. Okada, G. Fujita, T. Onoye, I. Shirakawa, ``An Error Concealment Algorithm Using Motion Estimation Method for MPEG-4 Video,'' TECHNICAL REPORT OF IEICE, DSP2000-107, pp. 37--43, October 2000.; [151] T. Song, H. S. Song, G. Fujita, T. Onoye, I. Shirakawa, ``A Codec of H.263 Advanced Intra Coding Mode and It's Architecture,'' TECHNICAL REPORT OF IEICE, DSP2000-107, pp. 45--50, October 2000.; [152] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, I. Shirakawa, ``Object Communication Scheme for Heterogeneous Environment,'' DICOMO 2002 Symposium, pp. 197--200, July 2000.; [153] W. Kobayashi, N. Sakamoto, T. Onoye, I. Shirakawa, ``3D Sound Localization Real-Time Algorithm and Its Low Power DSP Implementation,'' TECHNICAL REPORT OF IEICE, CAS2000-13, pp. 97--102, June 2000.; [154] R. Kuroda, G. Fujita, T. Onoye, I. Shirakawa, ``A VLSI Architecture for Shape-Adaptive Descrete Cosine Transformer Dedicated to MPEG-4 Video Codec,'' TECHNICAL REPORT OF IEICE, CAS2000-14, pp. 103--108, June 2000.; [155] Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, ``VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem,'' IEICE The 13th Karuizawa Workshop on Circuits and Systems, pp. 367--372, April 2000.; [156] S. Yamada, M. H. Miki, G. Fujita, T. Onoye, I. Shirakawa, ``Hardware-Based Bit-Rate Control for Low Bit-Rate Video Coding,'' IEICE The 13th Karuizawa Workshop on Circuits and Systems, pp. 385--390, April 2000.; [157] T. Watanabe, N. Ishiura, M Yamaguchi, ``A Code Generation Method for Datapath Oriented Codesign of Application Specific DSPs,'' IEICE The 13th Karuizawa Workshop on Circuits and Systems, pp. 539--544, April 2000.; [158] A. Niwa, S. Hashimoto, H. Okuhata, T. Onoye, I. Shirakawa, ``A VLSI Implementation of Portable MPEG-4 Audio Decoder,'' The 14th Digital Signal Processor Symposium, pp. 629--634, November 1999.; [159] Z. Andales, Y. Mitsuyama, K. Asari, T. Onoye, I. Shirakawa, ``An Approach to Reconfigurable Hardware-Based Cryptosystems,'' TECHNICAL REPORT OF IEICE, CAS99-63, NLP99-87, pp. 7--14, September 1999.; [160] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, I. Shirakawa, ``Array Cell Architecture for NMOS 4-Phase Dynamic Logic,'' TECHNICAL REPORT OF IEICE, CAS99-62, NLP99-86, pp. 1--6, September 1999.; [161] M.H.Miki, S. Yamada, G. Fujita, T. Onoye, I. Shirakawa, ``Low-Power Implementation of H.263 Codec for Mobile Computing,'' DA Symposium '99, pp. 183--188, July 1999.; [162] M. Furuie, K. Matsumura, G. Fujita, T. Masaki, I. Shirakawa, H. Inada, ``LSI Implementation of Wireless Data System Controller for Medical Cares,'' TECHNICAL REPORT OF IEICE, CAS99-32, pp. 15--19, June 1999.; [163] R.Y.Omaki, G.Fujita, T.Onoye, I.Shirakawa, ``A Video Coder Architecture Based on Discrete Wavelet Transform,'' TECHNICAL REPORT OF IEICE, CAS99-33, pp. 21--28, June 1999.; [164] M. Takahashi, N. Ishiura, A. Yamada, T. Kambe, ``Thread Partitioning Method for Hardware Compiler Bach,'' IEICE The 12th Karuizawa Workshop on Circuits and Systems, pp. 103--108, April 1999.; [165] T. Watanabe, N. Ishiura, M Yamaguchi, ``Scheduling Algorithm of Retargetable Compiler for Non-Orthogonal Datapaths,'' IEICE The 12th Karuizawa Workshop on Circuits and Systems, pp. 109--114, April 1999.; [166] M. Hatanaka, T. Masaki, T. Onoye, K. Murakami, ``VLSI Architecture of Switching Control for AAL Type2 Switch,'' IEICE The 12th Karuizawa Workshop on Circuits and Systems, pp. 427--432, April 1999.; [167] Y. Hattori, N. Ishiura, M Yamaguch, ``Operation and Transfer Binding of Retargetable Compilation for DSP,'' TECNICAL REPORT OF IEICE, VLD98-125, vol. 98, no. 447, pp. 55-61, December 1998.; [168] H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, I. Shirakawa, ``Function Modules for Video Decoding and Computer Graphics,'' TECHNICAL REPORT OF IEICE, VLD98-41, pp. 31--38, September 1998.; [169] D. Taki, M. H. Miki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, T. Kasami, ``VLSI Implementation of a Recursive Maximum Likelihood Decoder Dedicated to High-Speed Satellite Communication,'' TECHNICAL REPORT OF IEICE, VLD98-52, pp. 57--62, September 1998.; [170] Y. Mitsuyama, K. Asari, T. Onoye, I. Shirakawa, T. Baba, T. Ohtsuki, ``Reconfigurable Logic Based on Ferroelectric Non-Volatile Memory,'' TECHNICAL REPORT OF IEICE, ICD98-119, pp. 53--58, August 1998.; [171] Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, I. Shirakawa, ``VLSI Implementation of Function Module for Texture Mapping and Motion Compensation,'' TECHNICAL REPORT OF IEICE, VLD98-33, pp. 19--26, July 1998.; [172] Morgan H. Miki, Gen Fujita, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa, ``Low-Power Implementation of H.324 Audiovisual Codec for Mobile Computing,'' IEICE The 11th Karuizawa Workshop on Circuits and Systems, pp. 439--444, April 1998.; [173] Y. Takemoto, H. Fujishima, T. Onoye, I. Shirakawa, ``An Architecture of Matrix-Vector Multiplier Dedicated to Video Decoding and Three-Dimensional Computer Graphics,'' IEICE The 11th Karuizawa Workshop on Circuits and Systems, pp. 451--456, April 1998.; [174] M. Yamaguchi, N. ishiura, T. Kambe, ``A Binding Algorithm for Retargetable Compiler to Non-Orthogonal Datapaths,'' IEICE The 11th Karuizawa Workshop on Circuits and Systems, pp. 481--486, April 1998.; [175] H. Okuhata, M. Y. Morgan, T. Onoye, I. Shirakawa, ``A Low-Power DSP for Low Bitrate Speech Code,'' The 12th Digital Singal Processor Symposium, pp. 651-655, November 1997.; [176] H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, ``An Architecture of Unified Media-Processor Dedicated to Video Coding and Computer Graphics,'' The 2th Image Media-Processor Symposium, pp. 23-24, October 1997.; [177] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, I. Shirakawa, ``Implementation of Encoder-Decoder for Low Bitrate Visual Communication Dedicated to Mobile Computing,'' Technical Report of IEICE, DSP97-107, vol. 97, no. 315, pp. 17-24, October 1997.; [178] G. Fujita, M. H. Morgan, T. Onoye, I. Shirakawa, ``VLSI Implementation of H.263 Video Coding Dedicated to Mobile Computing,'' The 12th Image Encoding Symposium, pp. 51-52, October 1997.; [179] M. Yamaguchi, N. Ishiura, T. Kambe;, ``A Method of Retargetable Compilation for Embedded Systems,'' Technical Report of IEICE, VLD97-90, FTS97-53, pp. 85-92, October 1997.; [180] T. Yamamoto, N. Ishiura, M. Yamaguchi, Y. Hattori;, ``A High-Level Synthesis System for Embeded System,'' Technical Report of IEICE, VLD97-91, FTS97-54, pp. 93-99, October 1997.; [181] S. Sawa, A. Nagao, I. Shirakawa, T. Kambe, K. Chihara, ``Layout for MMICs Based on Rectangle-Packing,'' Technical Report of IEICE, VLD97-97, FTS97-60, pp. 141-146, October 1997.; [182] 荒井正, 水谷宣明, 会津隆士, 近藤仁志, ``GPSを用いた連続変位量観測による地すべり移動特性について\ ---長野県倉並地すべりの例---,'' 第36回地すべり学会研究発表講演集, pp. 365-368, August 1997.; [183] S. Sawa, A. Nagao, T. Kambe, I. Shirakawa, K. Chihara, ``A Method for Rectangle Packing Problem,'' IEICE Technical Report, DSP97-53, pp. 159-166, June 1997.; [184] S. Yano, N. Ishiura, ``Testing Embedded Memory Array Through a Scannable Configuration,'' IEICE The 10th Karuizawa Workshop on Circuits and Systems, pp. 95-100, April 1997.; [185] A. Nagao, T. Sawa, M. Isobe, T. Kambe, I. Shirakawa, ``A Layout Approach Dedicated to Monolithic Microwave IC,'' IEICE The 10th Karuizawa Workshop on Circuits and Systems, pp. 433-438, April 1997.; [186] M. Masaki, Y. Nakatani, T.Onoye, K. Murakami, ``Voice Communication on Multimedia ATM Network and Its VLSI Implementation,'' Technical Report of IEICE, IN97-10, pp. 39-46, April 1997.; [187] 清水則一, 近藤仁志, 宮下耕一, 小野浩, ``GPS地盤変位モニタリングシステムによる残壁の長期観測実験,'' 第28回岩盤力学に関するシンポジウム講演論文集, pp. 388-392, January 1997.; [188] 山口雅之, 中岡敏博, 神戸尚志, ``データパス構成と並列制約にもとづくアーキテクチャ評価システム,'' 電子情報通信学会技術研究報告, VLD96-74, CPSY96-86, pp. 71-78, December 1996.; [189] 中谷泰寛, 正城敏博, 尾上孝雄, 村上孝三, ``VCI 共有セルを用いたマルチメディア ATM 通信手法と VLSI 設計,'' 電子情報通信学会技術研究報告, DSP96-90, vol. 96, no. 301, pp. 39-46, October 1996.; [190] 宮野鼻晃士, 藤田玄, 尾上孝雄, 白川功, ``低ビットレート画像符号化アルゴリズムとその VLSI 化設計,'' 電子情報通信学会技術研究報告, DSP96-89, vol. 96, no. 301, pp. 33-38, October 1996.; [191] 森川俊, 岡田圭介, 竹内澄高, 白川功, ``高性能定係数FIRフィルタのVLSI化設計,'' 情報処理学会DAシンポジウム'96, pp. 41-46, August 1996.; [192] 佐藤洋, 森本康夫, 正城敏博, 尾上孝雄, 白川功, ``1チップ MPEG2 デコーダの設計と動き補償器の VLSI 実装,'' 情報処理学会DAシンポジウム'96, pp. 47-52, August 1996.; [193] 近藤仁志, ``GPSの地すべり計測への応用,'' 第40回システム制御学会研究発表講演会 (チュートリアルセッション), pp. 15-20, May 1996.; [194] 清水則一, 小野浩, 近藤仁志, 水田義明, ``長大残壁の安全監視へのGPS変位計測システムの応用に関する現場実験,'' 資源と素材, vol. 112, pp. 283-288, May 1996.; [195] 森川俊, 岡田圭介, 竹内澄高, 白川功, ``ディジタル映像伝送向け高性能FIRフィルタのVLSI化設計,'' 電子情報通信学会第9回回路とシステム軽井沢ワークショップ, pp. 359-364, April 1996.; [196] S. Yano, K. Akagi, and N. Ishiura, ``A New Scan Path Approach to Memory Array Testing,'' In 電子情報通信学会第9回回路とシステム軽井沢ワークショップ, pp. 55-60, April 1996.
Book: [1] M. Hashimoto and R. Nair, ``Power Integrity for Nanoscale Integrated Systems,'' McGraw-Hill Professional, February 2014.; [2] 伊藤雄一, 中島康祐, “ふさふさ”感触マルチタッチディスプレイの開発, 株式会社エヌ・ティー・エス, 2013.; [3] 伊藤雄一, 中島康祐, 「ふさふさ」した触り心地を実現する光ファイバによる毛状マルチタッチディスプレイ, 株式会社技術情報協会, 2013.
Article: [1] 佐藤高史, 橋本昌宜, ``経時劣化概説,'' 信頼性学会誌, vol. 35, no. 8, pp. 457--458, December 2013.; [2] 橋本昌宜, ``超低電力サブスレッショルド回路設計技術 ,'' IEICE Fundamentals Review, pp. 30--37, July 2013.; [3] 清川清, 畠中理英, 細田一史, 岡田雅司, 繁田浩功, 石原靖哲, 大下福仁, 角川裕次, 栗原聡, 森山甲一, ``オーエンス・ルイス：アンビエント環境制御を用いた知的オフィスチェアの提案,'' システム制御情報学会誌, vol. 56, no. 1, pp. 14-20, January 2012.; [4] 伊藤雄一, 中島康祐, ``～「ふさふさ」した触り心地～光ファイバによる毛状マルチタッチディスプレイ,'' MATERIAL STAGE, vol. 11, no. 8, pp. 13-16, November 2011.; [5] 橋本昌宜, ``遅延ばらつきを考慮したVLSIタイミング検証,'' エレクトロニクス実装学会誌, vol. 11, no. 3, pp. 182--185, May 2008.
IEICE Spring and Fall Conferences etc: [1] Yuki Tsujimoto, Yuichi Itoh, Takao Onoye, ``A Study on the Method for Thickness Control of an Interactive Display with Water Condensation,'' 情報処理学会インタラクション2017論文集, pp. 053-058, 2017.; [2] Mayu Yamashita, Taichi Fukamach, Ryoya Kachi, Adam Myers, Jesse Marciano, Yuichi Itoh, ``Ocuduss: Speed Sensation Presentation Device by Optical Flow Control,'' 情報処理学会インタラクション2017論文集, pp. 745-748, 2017.; [3] 山下真由, 伊藤雄一, 石原好貴, 上田将理, 綛田峰矢, 尾上孝雄 , ``KeyPressense: キーの押下開始タイミングを検知できるキーボード,'' エンタテインメントコンピューティングシンポジウム2017論文集, vol. 2017, pp. 298-300, 2017.; [4] 佐藤雅紘, 飯塚翔一, 粟野皓光, 橋本昌宜, 尾上孝雄, ``NBTIによる閾値電圧変化の確率的モデル化に関する一考察,'' 2015年電子情報通信学会総合大会講演論文集, March 2015.; [5] 河野仁, 橋本昌宜, 近藤利彦, 森村浩季, ``超小型コイルを用いた近距離無線通信における周辺コイルの影響評価,'' 2015年電子情報通信学会総合大会講演論文集, March 2015.; [6] 益田涼平, 橋本昌宜, 尾上孝雄, ``サーモパイル型赤外線センサを用いた人感センサの性能評価,'' 2015年電子情報通信学会総合大会講演論文集, March 2015.; [7] 宮崎陽平, 伊藤雄一, 藤原健, 高嶋和毅, 尾上孝雄, ``SenseChairによる会話者間の同調傾向検出,'' 情報処理学会インタラクション2015論文集, March 2015.; [8] 安藤正宏, 細井俊輝, 伊藤雄一, 高嶋和毅, 北村喜文, ``StackBlock: 積み重ね形状認識可能なブロック型UI,'' 情報処理学会インタラクション論文集, 2015.; [9] 宮崎陽平, 伊藤雄一, 藤原健, 高嶋和毅, 尾上孝雄, ``SenseChairを用いた眠気検出に関する検討,'' 情報処理学会インタラクション2014論文集, March 2014.; [10] 安藤正宏, 細井俊輝, 中島康祐, 高嶋和毅, 伊藤雄一, 足立智昭, 尾上孝雄, 北村喜文, ``StackBlock: 積み重ね形状構築を可能とするブロック型デバイス,'' 情報処理学会インタラクション論文集, pp. 135-142, 2014.; [11] 宮崎陽平, 安藤正宏, 藤田悠矢, 羽鹿諒, Ondreicka Merrielle, 伊藤雄一, ``ケツログラフィティ: 結露を用いたインタラクティブディスプレイ,'' EC2013, October 2013.; [12] 中川雄太, 岸野文郎, 中島康祐, 伊藤雄一, ``半球状の毛状マルチタッチディスプレイにおけるタッチインタラクション認識,'' 日本バーチャルリアリティ学会第18回大会論文集, pp. 659-660, September 2013.; [13] 井藤佑哉, 岸野文郎, 中島康祐, 伊藤雄一, ``毛状ディスプレイの特定領域内での触感変化に関する検討,'' 日本バーチャルリアリティ学会第18回大会論文集, pp. 390-391, September 2013.; [14] 作田賢志朗, 安部晋一郎, 渡辺幸信, 原田諒, 橋本昌宜, 更田裕司, 上村大樹, ``宇宙線中性子起因マルチセルアップセットのスケーリング則調査,'' 応用物理学会秋期学術講演会, September 2013.; [15] 根本祐輔, 中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``吹きかけインタラクションのための入力検出法の検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 213, March 2013. (A-16-7); [16] 富田健太郎, 中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``毛状ディスプレイの触感変化に関する検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 214, March 2013. (A-16-8); [17] 内田將太郎, 岸野文郎, 池田和章, 中島康祐, 伊藤雄一, ``SenseChairを用いた眠気検出に関する検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 215, March 2013. (A-16-9); [18] M. Okada, M. Hatanaka, T. Onoye, ``Realization of Secure Ambient Wireless Network System Based on Spatially Distributed Ciphering Function,'' 第14回 DSPS教育会議予稿集, pp. 71-72, September 2012.; [19] 藤本拓, 伊藤雄一, 石原のぞみ, 中島康祐, 尾上孝雄, ``タブレットデバイスと目の位置関係を考慮した電子書籍表示手法に関する検討,'' ヒューマンインタフェースシンポジウム2012論文集, pp. 701-704, September 2012.; [20] 中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``半球状の毛状マルチタッチディスプレイ,'' 日本バーチャルリアリティ学会第17回大会論文集, pp. 300-303, September 2012.; [21] 藤井佑一, 岸野文郎, 藤田和之, 中島康祐, 伊藤雄一, 菊池日出男, ``U-brella: 降り注ぐ情報を可振化するポータブル傘型インタフェース,'' 日本バーチャルリアリティ学会第17回大会論文集, pp. 652-655, September 2012.; [22] 上野美保, 橋本昌宜, 尾上孝雄, ``電気的タイミング故障のデバッグ向けオンチップリアルタイム電源電圧センサ,'' 電子情報通信学会2009ソサイエティ大会2012, vol. A-3-6, p. 53, September 2012.; [23] M. Okada, T. Onoye, W. Kobayashi, ``An Interactive System of Sound Field Auralization with GPU Ray Tracer and Efficient HRTF Filtering,'' 電子情報通信学会総合大会, A-20-7, March 2012.; [24] 竹中拓也, 岸野文郎, 藤田和之, 中島康祐, 伊藤雄一, ``二者間の着座状態と会話の活性度の関係に関する検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 220, March 2012. (A-14-2); [25] 中川雄太, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``立体毛状マルチタッチディスプレイの一検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 261, March 2012. (A-16-12); [26] 川幡尚亮, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``インテリアへの適用を考慮した毛状ディスプレイの耐荷重に関する検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 262, March 2012. (A-16-13); [27] 金田征悟, 藤井佑一, 岸野文郎, 中島康祐, 伊藤雄一, ``毛状ディスプレイのための吹きかけインタラクションの検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 263, March 2012. (A-16-14); [28] 藤枝智子, 岸野文郎, 中島康祐, 池田和章, 伊藤雄一, ``着座姿勢の歪みを是正するシステムに向けたセンシングの基礎検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 266, March 2012. (A-16-17); [29] 菊地佑介, 岸野文郎, 石原のぞみ, 中島康祐, 伊藤雄一, ``形容詞クエリを用いた連想意味関係の名詞抽出に関する検討,'' 電子情報通信学会総合大会講演論文集（基礎・境界）, p. 267, March 2012. (A-16-18); [30] 清川清, 畠中理英, 細田一史, 岡田雅司, 繁田浩功, 石原靖哲, 大下福仁, 角川裕次, 栗原聡, 森山甲一, ``オーエンス・ルイス－アンビエント環境制御を用いた知的オフィスチェアの開発－,'' ヒューマンインターフェースシンポジウム, September 2011.; [31] 中瀬絢哉, 栗原聡, 森山甲一, 石原靖哲, 大下福仁, 角川裕次, 清川清, 畠中理英, 細田一史., ``カフェ・ド・ナイーダ：アンビエント環境における最適インタラクション推定機構の提案,'' ヒューマンインターフェースシンポジウム, September 2011.; [32] Yusuke Hayashi, Yuichi Itoh, Kosuke Nakajima, Kazuyuki Fujita, Kazuki Takashima, Ikuo Daibo, Takao Onoye, ``Cup-Le: a Cup-Shaped Device for Conversational Experiment,'' ヒューマンインターフェースシンポジウム2011論文集, September 2011.; [33] 藤田和之, 高嶋和毅, 伊藤雄一, 大崎博之, 小野直亮, 香川景一郎, 津川翔, 中島康祐, ``Ambient Suite: 部屋型情報空間を用いた対人コミュニケーション支援,'' ヒューマンインタフェースシンポジウム2011論文集, pp. 395-400, September 2011.; [34] R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, S. Sampei, ``Fpga Implementation of Ofdm Baseband Transceiver with Dynamic Spectrum Access,'' The General Conference of IEICE, AS-2-2, March 2010.; [35] 中村秀幸, 筒井弘, 橋本亮司, 尾上孝雄, ``特徴点追跡を用いた動き補償フレーム補間手法,'' 電子情報通信学会2009ソサイエティ大会, A-20-14, p. 204, September 2009.; [36] R. Hashimoto, K. Kato, G. Fujita, T. Onoye, ``Performance Enhancement of Cabac Decoder for H.264/Avc,'' 電子情報通信学会2008ソサイエティ大会,A-20-9, September 2008.; [37] 橋本亮司, 藤田玄, 尾上孝雄, ``1080HD向けH.264 CAVLC復号器の高速化に関する一検討,'' 電子情報通信学会2007ソサイエティ大会,A-20-16, September 2007.; [38] Seiichi YAMAZAKI, Yukio MITSUYAMA, Takao ONOYE, ``An Approach to Automatic Stroke Modification Based on Gravity Center of Characters,'' 2007 IEICE Society Conference, A-20-13, September 2007.; [39] Hiroshi Tsutsui, ``Video Coding Scheme for Video Sequences Degraded by Noise of Old Motion Picture Films,'' 電子情報通信学会2007ソサイエティ大会, AK-2-3, September 2007. (2007年電子情報通信学会ソサイエティ大会基礎・境界ソサイエティ特別企画「若手研究者のための映像圧縮コンテスト」最優秀賞受賞); [40] T. Enami, M. Hashimoto, ``Adaptive Spatial Division for Statistical Modeling of Power Supply Noise,'' Proc. The Society Conference of IEICE, pp. A-3-10, September 2007.; [41] 河村侑輝, 橋本亮司, 尾上孝雄, ``H.264符号化における1/4画素精度動き検出の性能評価,'' 電子情報通信学会2007ソサイエティ大会,A-4-28, September 2007.; [42] Ryoji Hashimoto, Tomoya Matsumura, Yoshihiro Nozato, Kenji Watanabe, Takao Onoye, ``Implementation of Object Attention System Based on Compound-Eye Sensor,'' Proceedings of 9th DSPS Educators Conference, pp. 87-88, August 2007.; [43] Shinyu Ninomiya, Masanori Hashimoto, ``Accuracy of SSTA Considering Spatial Correlations and Number of Spatial Divisions,'' Proc. The General Conference of IEICE, A-3-1, March 2007.; [44] K. Hamamoto, M. Hashimoto, Y. Mitsuyama, T. Onoye, ``Area Efficiency Evaluation of Body-Biasing Layout Styles for Low Voltage Circuits,'' Proc. The General Conference of IEICE, A-3-6, March 2007.; [45] S. Abe, M. Hashimoto, T. Onoye, ``Evaluation of Clock Skew in Mesh Style Clock Distribution,'' Proc. The General Conference of IEICE, A-3-5, March 2007.; [46] H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye, ``A Study on Design Policy for Subthreshold Circuits with Adders,'' Proc. The General Conference of IEICE, A-3-17, March 2007.; [47] Siriporn Jangsombatsiri, Masanori Hashimoto, Ryo Tsuchiya, Haikun Zhu, Chung-Kuan Cheng, ``Eye-Pattern Evaluation of On-Chip Interconnects with Intentional Shunt Conductance,'' Proc. The General Conference of IEICE, A-3-9, March 2007.; [48] K. Shinkai, M. Hashimoto, T. Onoye, ``Future Prediction of Self-Heating in Short Intra-Block Wires,'' The Society Conference of IEICE, pp. A-3-14, September 2006.; [49] K. Kato, R. Hashimoto, G. Fujita, T. Onoye, ``Intra Prediction Mode Decision Scheme for H.264 Based on Temporally and Spatially Adjacent Header Information,'' Proc. The Society Conference of IEICE, A-4-12, September 2006.; [50] Mohd Nadzrul Mohd Nor, Tomoya Matsumura, and Takao Onoye, ``Improvement of Direction of Arrival Estimation of Speech Using Two-Channel Microphone Array with Angle Position Realignment,'' In IEICE Society Conference, A-4-32, September 2006.; [51] T. Enami, M. Hashimoto, T. Onoye, ``Evaluation of Active Circuit Modeling for Power Noise Analysis,'' Proc. The General Conference of IEICE, A-3-16, March 2006.; [52] R. Hashimoto, G. Fujita, T. Onoye, ``An Approach to H.264 Encoding Parameter Selection Based on Amount of Motion,'' Proc. The General Conference of IEICE, D-11-42, March 2006.; [53] 高橋真吾, 築山修治, 橋本昌宜, 白川功, ``液晶ディスプレイ用サンプリング回路の設計手法について,'' 2005 年電子情報通信学会ソサイエティ大会講演論文集, A-3-4, 2005.; [54] Y. Shigenobu, T. Onoye, I. Shirakawa, ``An MPEG-2/{mpeg}-4 Transcoding Method Based on Information from MPEG-2 Coded Bitstreams,'' IEICE The 19th SIP Symposium, D4-4, November 2004.; [55] T. Imanaka, G. Fujita, T. Onoye, I. Shirakawa, ``Real-Time Human Object Extraction Method for Mobile Use,'' IEICE The 19th SIP Symposium, D1-3, November 2004.; [56] A. Kosaka, H. Okuyata, T. Onoye, I. Shirakawa, ``Design of Ogg Vorbis Decoder System for Embedded Platform,'' IEICE the 19th Symposium on Signal Processing, C7-1, November 2004.; [57] K. Watanabe, H. Nishida, G. Fujita, T. Onoye, I. Shirakawa, ``Home Network Control System Based on Agent Technology,'' Proc. The Society Conference of IEICE, A-1-30, September 2004.; [58] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa, ``Parasitic Capacitance Extraction Method for System LCD Circuits,'' Proc. The Society Conference of IEICE, A-1-16, September 2004.; [59] H. Okuhata, A. Kosaka, T. Matsumura, T. Onoye, I. Shirakawa, ``Reduced Complexity Multi-Scale Retinex for Realtime Video System,'' Proc. The Society Conference of IEICE, A-4-22, September 2004.; [60] M. Kawakita, G. Fujita, T. Onoye, I. Shirakawa, ``Implementation of Realtime JPEG - MPEG-4 Transcoder,'' Proc. The Society Conference of IEICE, A-4-7, March 2004.; [61] Y. D. Handoko, T. Song, G. Fujita, T. Onoye, I. Shirakawa, ``VLSI Design of Low Complexity Motion Estimation Algorithm TS-{me} for H.264,'' Proc. The Society Conference of IEICE, A-4-10, March 2004.; [62] Katsuya Nakagawa, Masaru Kawakita, Takao Onoye, Toru Chiba, Isao Shirakawa, ``Discussion on Usability of Adaptive Information Space Liaison,'' IPSJ and IEICE The 2nd Forum on Information Technology, vol. 4, pp. 267--268, September 2003.; [63] M. Kimura, Y. Mitsuyama, T. Onoye, I. Shirakawa, ``Architecture of Cipher Algorithms for Wireless LAN Enhanced Security Standard,'' in Proc. of the 2003 IEICE Society Conference, A-4-4, September 2003.; [64] T. Imanaka, K. Hontani, G. Fujita, T. Onoye, I. Shirakawa, ``Real-Time Hair Object Detection and Extraction for Video Phone,'' Proc. The Society Conference of IEICE, A-4-26, September 2003.; [65] S. Maeta, S. Yamaguchi, A. Kosaka, H. Okuhata, A. Yamada, T. Onoye, I.Shirakawa, ``VLSI Implementation of Ogg Vorbis Decoder Using Bach C Language,'' Proc. The Society Conference of IEICE, A-3-8, March 2003.; [66] N. Iwanaga, N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa, ``Embedded Implementation of 'out-Of-Head' Acoustic Field Enhancement for Stereo Headphones,'' Proc. The Society Conference of IEICE, A-4-20, September 2002.; [67] T. Uchida, T. Okada, T. Onoye, I. Shirakawa, ``Implementation of Pseudo Random Noise Code Generator for GNSS Receiver,'' Proc. The Society Conference of IEICE, A-5-15, September 2002.; [68] M. Ise, Y. Uchida, T. Onoye, I. Shirakawa, ``A Layered Digital Matched Filter for W-CDMA,'' Proc. The Society Conference of IEICE, A-1-7, September 2001.; [69] Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, ``VLSI Architecture of Turbo Code for W-CDMA,'' Proc. The Society Conference of IEICE, A-1-8, September 2001.; [70] M. H. Miki, M. Sakamoto, N. Kawahara, Y. Takeuchi, T. Yoshida, I. Shirakawa, ``An Efficient Executable File Compaction and Its Execution Method for Embedded Systems,'' Proc. The Society Conference of IEICE, A-3-15, September 2001.; [71] N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa, ``Hardware Implementation of 3D Sound Localization System for Monaural Sound Source,'' Proc. The Society Conference of IEICE, A-4-40, September 2001.; [72] T. Nakagawa, S. Hamanaka, G. Fujita, I. Shirakawa, ``VLSI Implementation of Padding Processing for MPEG-4 Video Coding,'' Proc. The Society Conference of IEICE, A-4-41, September 2001.; [73] H. Kobayashi, H. Mizuno, T. Onoye, I. Shirakawa, ``Power Estimation Method for Embedded Systems,'' Proc. The Society Conference of IEICE, SA-1-1, September 2001.; [74] A. E. Shiitev, H. Okada, H. S. Song, G. Fujita, T. Onoye, I. Shirakawa, ``A Study on Error Detection Using Digital Watermarking for MPEG-4 Video Transmission,'' Proc. The Society Conference of IEICE, D-11-38, September 2001.; [75] H. Okada, H. S. Song, G. Fujita, T. Onoye, I. Shirakawa, ``Error Detection Using Digital Watermark for MPEG-4 Video Coding,'' Proc. Visual Computing 2001, pp. 19--20, June 2001.; [76] G. Raja, T. Song, G. Fujita, T. Onoye, I. Shirakawa, ``VLSI Design of Deblocking Filter and Advanced Intra Coding for H.263,'' Proc. The Society Conference of IEICE, A-3-7, March 2001.; [77] S. Yamaguchi, A. Kosaka, H. Okuhata, I. Shirakawa, ``VLSI Implementation of Ogg Vorbis Decoder for Embedded Processor,'' Proc. The Society Conference of IEICE, A-3-8, March 2001.; [78] S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa, ``Implementation of 3D Sound Movement by Embedded DSP,'' Proc. The Society Conference of IEICE, A-4-55, March 2001.; [79] Y. Mitsuyama, N. Iwanaga, T. Onoye, I. Shirakawa, ``Scatternet Formation and Efficient Routing Control for Bluetooth-Based Ad Hoc Networks,'' Proc. The Society Conference of IEICE, A-4-68, March 2001.; [80] K. Hontani, G. Fujita, I. Shirakawa, ``Modified SNAKES for Realtime Face Object Extraction,'' Proc. The Society Conference of IEICE, D-12-15, March 2001.; [81] S. Komata, W. Kobayashi, N. Sakamoto, T. Onoye, I. Shirakawa, ``Realtime 3Dsound Localization Algorithm for Embedded DSP Implementati on,'' ITE Winter Annual Convention 2000, 1-11, December 2000.; [82] M. H. Miki, T. Onoye, I. Shirakawa, ``VLSI Implementation of Java Accelerator for Embedded Processors,'' Proc. The Society Conference of IEICE, A-3-12, October 2000.; [83] T. Watanabe, N. Ishiura, ``Minimization of Spill Code Insertion for Code Generation for Application Specific DSPs,'' Proc. The Society Conference of IEICE, A-3-20, October 2000.; [84] W. Kobayashi, N. Sakamoto, T. Onoye, I. Shirakawa, ``A Realtime Algorithm for Three Dimensional Sound Localization,'' Proc. The Society Conference of IEICE, A-4-23, October 2000.; [85] S. Hamanaka, R. Kuroda, G. Fujita, I. Shirakawa, ``VLSI Implementation of Reversible Length Decode Core,'' Proc. The Society Conference of IEICE, A-4-41, October 2000.; [86] Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, ``A Cryptosystem Based on Reconfigurable Hardware,'' Proc. The Society Conference of IEICE, A-4-42, October 2000.; [87] S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, I. Shirakawa, ``VLSI Implementation of Noiseless Decoding and Prediction Cores for MPEG-4 Audio Decoder,'' Proc. The Society Conference of IEICE, A-3-4, September 1999.; [88] M. Oshita, T. Onoye, I. Shirakawa, ``High Speed Implementation of JBIG Arithmetic Coder,'' Proc. The General Conference of IEICE, A-4-32, March 1999.; [89] S. Yamada, M. H. Miki, G. Fujita, T. Onoye, I. Shirakawa, ``Bit-Rate Control Algorithm for H.263 Coding,'' Proc. The Society Conference of IEICE, B-8-31, October 1998.; [90] Y. Takemoto, H. Fujishima, T. Onoye, I. Shirakawa, ``Hybrid Matrix-Vector Multiplier for Video Decoding and 3-Dimensional Computar Graphics,'' Proc. The General Conference of IEICE, C-12-19, May 1998.; [91] N. Ishiura, M. Yamaguchi, ``Compression of Instruction COdes for Application Specific VLSW Processos,'' in Proc. The Society conference of IEICE, A-3-10, August 1997.; [92] G. Fujita, T. Onoye, I. Shirakawa, ``VLSI Im;Ementation of DCT/{idct} COre for H.263 Nideo Coding,'' in Proc. The Society conference of IEICE, C-12-28, August 1997.; [93] K. Miyanohana, K. Yanagida, T. Onoye, I. Shirakawa, ``VLSI Implementation of Low Bitrate Visual Communication System,'' in Proc. The 41th Annual Conference of ISCIE, pp. 247-248, May 1997.; [94] 森川俊, 岡田圭介, 竹内澄高, 白川功, ``映像伝送用高性能ディジタルフィルタの VLSI 化設計,'' 電子情報通信学会総合大会, A-4-29, March 1997.; [95] 藤田玄, Itthichai Arungsrisangchai, 尾上孝雄, 白川功, ``H.263 向け動き検出器の VLSI 化設計,'' 電子情報通信学会総合大会, SC-11-2, March 1997.; [96] 正城敏博, 中谷泰寛, 尾上孝雄, 村上孝三, ``VCI 共有セルを用いた ATM 音声通信手法,'' 電子情報通信学会ソサイエティ大会, SB-10-2, September 1996.; [97] 吉田幸宏, 宋宝玉, 奥畑宏之, 尾上孝雄, 白川功, ``組み込み用プロセッサの低消費電力化に対する一手法,'' 電子情報通信学会ソサイアティ大会, SA-1-2, September 1996.; [98] 中岡敏博, 山口雅之, 山田晃久, 神戸尚志, ``評価システムを用いたプログラム方式専用プロセッサの設計支援,'' 情報処理学会第53回全国大会, 2B-1, pp. 21-22, September 1996.

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