論文誌
[1]  Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Supply Noise Suppression by Triple-Well Structure,'' IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp. 781--785, April 2013.
[2]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform,'' IEEE Journal of Solid-State Circuits, vol. 44, no. 6, pp. 1745--1755, June 2009.
[3]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3461-3464, December 2008.
[4]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects,'' IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718-728, March 2008.
[5]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872, October 2007.
[6]  M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, ``Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4,'' International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.
[7]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect,'' In IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 4, pp. 724--731, April 2007.
[8]  M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``W-CDMA Channel Codec by Configurable Processors,'' In Intelligent Automation and Soft Computing, vol. 12, no. 3, pp. 317--29, 2006.
国際会議
[1]  Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to Sso,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pp. 19--20, May 2010.
[2]  Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 397--400, November 2008.
[3]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification,'' In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108, January 2008.
[4]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 783-786, September 2007.
[5]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' In Proc. IEEE European Solid-State Device Research Conference, pp. 115-118, September 2007.
[6]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects,'' Proc. IEEE International Conference on Computer Design, pp. 70--75, October 2006.
[7]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 721--724, September 2006.
[8]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation,'' In Proc.~IEEE Custom Integrated Circuits Conference, pp. 861--864, September 2006.
[9]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Delay Variation Due to Inductive Coupling,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 305--308, September 2005.
[10]  Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa, ``Architecture of Turbo Decoder for W-CDMA by Configurable Processor,'' In Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4, p. 7, July 2004.
[11]  M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``Implementation of W-CDMA Channel Codec by Configurable Processors,'' In Proc. Sixth Baiona Workshop on Signal Processing in Communications, pp. 205--210, September 2003.
研究会等発表論文
[1]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``バス配線による誘導性クロストークノイズによる遅延変動の実測とノイズ重ねあわせ効果の検証,'' , 信学技報, VLD2007-153, March 2008.
[2]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``スタンダードセルで構成された電源ノイズ波形測定回路の提案,'' 信学技報, CPM2007-131, ICD2007-142, pp. 17-22, January 2008.
[3]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測,'' 信学技報, CPM2006-131, ICD2006-173, pp. 13--18, January 2007.
[4]  小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄, ``電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法,'' 信学技報, CPM2006-132, ICD2006-174, pp. 19--23, January 2007.
[5]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``LSI配線における容量性, 誘導性クロストークノイズの定量的将来予測,'' 第19回回路とシステム軽井沢ワークショップ, pp. 5--10, April 2006.
[6]  伊勢正尚, 小笠原泰弘, 渡邊賢治, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``IEEE 802.15.4を用いたホームネットワーク向け無線ネットワークプロトコル,'' 信学技報, CAS2005-99, pp. 19--24, March 2006.
[7]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``誘導性・容量性クロストークノイズによる遅延変動の測定と評価,'' 信学技報, SDM2005-135, ICD2005-74, pp. 43--48, August 2005.
[8]  盧 承烈, 小笠原 泰弘, 伊勢 正尚, 畠中 理英, 尾上 孝雄, 庭本 浩明, 芥子 育雄, 白川 功, ``ユニバーサルプラグアンドプレイ技術を用いたホームネットワーク一構成方式,'' 信学技報, CAS2004-68, pp. 7--12, January 2005.

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