論文誌
[1]  H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518--2529, December 2014.
[2]  H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1468--1482, July 2014.
[3]  H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Nbti Mitigation Method by Inputting Random Scan-In Vectors in Standby Time,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1483--1491, July 2014.
[4]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1461--1467, July 2014.
[5]  D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, vol. 21, no. 12, p. 2165 -- 2178, December 2013.
[6]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement,'' IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 2630--2634, August 2013.
[7]  T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,'' IEICE Trans. on Information and Systems , vol. E96-D, no. 8, pp. 1624--1631, August 2013.
[8]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling,'' IEEE Transactions on Information Forensics and Security, vol. 8, no. 8, pp. 1331--1342, August 2013.
[9]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices,'' IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
[10]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 20, no. 2, pp. 333--343, February 2012.
[11]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating NBTI-Induced Delay Degradation,'' IEICE Trans. Fundamentals, vol. E94-A, no. 12, pp. 2545-2553, December 2011.
[12]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Transactions on Nuclear Science, vol. 58, no. 4, pp. 2097--2102, August 2011.
[13]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2417-2423, December 2010.
[14]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 18, no. 7, pp. 1118--1129, July 2010.
[15]  密山 幸男, 高橋 一真, 今井 林太郎, 橋本 昌宜, 尾上 孝雄, 白川 功, ``メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現,'' 電子情報通信学会論文誌, vol. J93-A, no. 6, pp. 397-413, June 2010.
[16]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3094-3102, December 2009.
[17]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Trans. on Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.
[18]  Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa, ``Area-Efficient Reconfigurable Architecture for Media Processin,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3651-3662, December 2008.
[19]  小谷 章夫, 種村 嘉高, 密山 幸男, 朝井 宣実, 中村 安久, 尾上 孝雄, ``ポテンシャルエネルギーを用いた文字重心位置取得手法,'' 画像電子学会誌, vol. 35, no. 4, pp. 296--305, July 2006.
[20]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp. 899-906, April 2005.
[21]  小谷 章夫, 小山 至幸, 密山 幸男, 尾上 孝雄, ``低解像度表示デバイス向けフォント "LCFONT" の重心位置および可読性評価,'' 画像電子学会誌, vol. 32, no. 5, pp. 621--628, September 2003.
[22]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A Novel Dynamically Reconfigurable Hardware-Based Cipher,'' 情報処理学会論文誌, vol. 42, no. 4, pp. 958--966, April 2001.
国際会議
[1]  R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, ``Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
[2]  M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 14--15, January 2015.
[3]  Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, and Takao Onoye, ``Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design,'' In ReConFig, December 2013.
[4]  D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 313-316, November 2013.
[5]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices,'' Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012.
[6]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of Nbti-­Induced Pulse-Width Modulation on Set Pulse-Width Measurement,'' Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.
[7]  T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.
[8]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2012.
[9]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures,'' In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pp. 189-194, September 2011.
[10]  Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, and Takao Onoye, ``Nbti Mitigation by Giving Random Scan-In Vectors during Standby Mode,'' In PATMOS2011, September 2011.
[11]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing,'' In Proc. International Reliability Physics Symposium (IRPS), April 2011.
[12]  D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability,'' In IEEE Workshop on Silicon Errors in Logic - System Effects, March 2011.
[13]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling,'' In Proc. International Workshop on Information Security Applications (WISA 2010), pp. 107-121, January 2011.
[14]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' In Proceedings of International Reliability Physics Symposium (IRPS), pp. 213--217, May 2010.
[15]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 646-651, March 2010.
[16]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), March 2010.
[17]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 361-362, January 2010.
[18]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Soft Error Resilient Vlsi Architecture for Signal Processing,'' In Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 183--186, December 2009.
[19]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 215-218, September 2009.
[20]  K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits,'' In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 51--56, August 2009.
[21]  D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.
[22]  Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 236--241, March 2009.
[23]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability,'' In Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
[24]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 266-271, January 2009.
[25]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits,'' In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.
[26]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits,'' In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, August 2008.
[27]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -,'' In ACM Great Lakes Symposium on VLSI, pp. 387-390, May 2008.
[28]  K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, ``A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 233-237, October 2007.
[29]  Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``Domain-Specific Reconfigurable Architecture for Media Processing,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2006), pp. 322--327, April 2006.
[30]  A. Kotani, Y. Tanemura, Y. Mitsuyama, Y. Asai, Y. Nakamura, and T. Onoye, ``Contour-Based Gravity Center Evaluation of Characters,'' In Proc. EUROMEDIA, pp. 15--20, April 2006.
[31]  Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing,'' In Proc. International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC2005), pp. 131--132, July 2005.
[32]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Embedded Architecture of IEEE802.11i Cipher Algorithms,'' In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pp. 241--246, September 2004.
[33]  A. Kotani, Y. Asai, Y. Nakamura, S. Okada, N. Koyama, K. Yamane, Y.Okano, Y. Mitsuyama, and T. Onoye, ``Visibility Font Technology on High Resolution Color LCD "LCFONT.c",'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003), Kang-Woo Do, Korea, vol. 1, pp. 535--538, July 2003.
[34]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``Burst Mode: a New Acceleration Mode for 128-Bit Block Ciphers,'' In in Proc. IEEE 24th Custom Integrated Circuits Conference (CICC2002), Orland, Florida, pp. 151--154, May 2002.
[35]  Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers,'' In ibid, vol. II, pp. 344--347, May 2002.
[36]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``System Performance Evaluation of High-Speed Burst Mode for 128-Bit Block Ciphers,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 332--339, October 2001.
[37]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers,'' In in Proc. 14th Annual IEEE International ASIC/SoC Conference (ASIC/SoC2001), Washington, D.C., pp. W.1.1.1--W.1.1.5, September 2001.
[38]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, vol. IV, pp. 734--737, May 2001.
[39]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A High Performance Burst Mode Approach for 128-Bit Block Ciphers,'' In in Proc. EUROMEDIA2001, Valencia, Spain, pp. 146--150, April 2001.
[40]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A Dynamically Reconfigurable Hardware-Based Cipher Chip,'' In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 11--12, January 2001.
[41]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Symposium on VLSI Circuits Digest of Technical Papers, Hawaii, USA, pp. 204--205, June 2000.
[42]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``Chameleon: a Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pp. 90--94, May 2000.
[43]  K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, ``Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware,'' In in Proc. IEEE Internatinal Solid-State Circuits Conference, pp. 106--107, February 1999.
研究会等発表論文
[1]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討,'' 信学技報, RECONF2013-8, vol. 113, no. 52, pp. 41-46, May 2013.
[2]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法,'' 信学技報, VLD2012-154, vol. 112, no. 451, pp. 099-104, March 2013.
[3]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的部分再構成による故障回避に関する一考察,'' 信学技報, RECONF2012-59 , vol. 112, no. 325, pp. 71-76, November 2012.
[4]  亀田 敏広, 郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``スキャンパスを用いたNBTI劣化抑制に関する研究,'' 情報処理学会DAシンポジウム, pp. 201-206, August 2011.
[5]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的再構成可能アーキテクチャによる故障回避機構の定量的評価,'' 信学技報, RECONF2011-6, vol. 111, no. 31, pp. 31-36, May 2011.
[6]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース物理乱数生成器の設計手法,'' 情報処理学会研究報告, SLDM2010-147, vol. 2010-SLDM-147, no. 19, pp. 1-6, November 2010.
[7]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``NBTI による劣化予測におけるトランジスタ動作確率算出法の評価,'' 情報処理学会DAシンポジウム, pp. 181-186, August 2009.
[8]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``マルコフモデルによるオシレータサンプリング方式真性乱数生成器の乱数品質解析,'' 第22回回路とシステム軽井沢ワークショップ, pp. 474-479, April 2009.
[9]  濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``レイアウトを考慮した基板バイアスクラスタリング手法,'' 信学技報, VLD2008-159 , vol. 108, no. 478, pp. 195-200, March 2009.
[10]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証,'' 信学技報, VLD2008-159, vol. 108, no. 478, pp. 201-206, March 2009.
[11]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析,'' 情報処理学会DAシンポジウム, pp. 217-222, August 2008.
[12]  濱本 浩一, 更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``基板バイアス印加レイアウト方式の面積効率と速度制御性の評価,'' 信学技報, CAS2008-14, VLD2008-27, SIP2008-48(2008-6), pp. 75-79, June 2008.
[13]  種村 嘉高, 小谷 章夫, 山崎 聖一, 密山 幸男, 尾上 孝雄, ``視覚特性を考慮した文字の黒み推定に関する一検討,'' 電子情報通信学会技術研究報告, vol. 106, no. 374, pp. 69--74, November 2006.
[14]  小谷 章夫, 種村 嘉高, 朝井 宣美, 中村 安久, 大塚 正章, 密山 幸男, 尾上 孝雄, ``文字重心位置評価手法とその可読性評価への応用,'' 信学技報, SIS2005-23, pp. 1--6, September 2005.
[15]  小谷 章夫, 朝井 宣美, 中村 安久, 大塚 正章, 密山 幸男, 尾上 孝雄, ``文字輪郭を用いた重心位置評価手法に関する一検討,'' 情報処理学会研究報告, 2004-HI-111, pp. 63--70, November 2004.
[16]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``組込みシステム向け IEEE802.11i 暗号処理回路の実装,'' 信学技報, ICD2004-129, pp. 49--54, October 2004.
[17]  今井 林太郎, 密山 幸男, 尾上 孝雄, 白川 功, ``メディア処理向けリコンフィギュラブルアーキテクチャに関する一検討,'' 電子情報通信学会 第4回リコンフィギャラブルシステム研究会, pp. 33--40, September 2004.
[18]  木村基, 密山幸男, 尾上孝雄, 白川功, ``組込みシステム向け IEEE 802.11i 暗号処理器のアーキテクチャ,'' 第17回回路とシステム軽井沢ワークショップ, pp. 217--222, April 2004.
[19]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``ブロック暗号の高速化暗号モードとその VLSI 化設計,'' 信学技報, CAS2001-41, pp. 89--94, June 2001.
[20]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A New Approach for 128-Bit Block Ciphers,'' In 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 231--236, April 2001.
[21]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いたハードウェア向き暗号方式,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 367--372, April 2000.
[22]  Zaldy ANDALES, 密山 幸男, 浅利 康二, 尾上 孝雄, 白川 功, ``リコンフィグラブルハードウェアを用いた暗号システム,'' 信学技報, CAS99-63, NLP99-87, pp. 7--14, September 1999.
[23]  密山 幸男, 浅利 康二, 尾上 孝雄, 白川 功, 馬場 孝明, 大槻 達男, ``強誘電体メモリを用いた Reconfigurable Logic とその性能評価,'' 信学技報, ICD98-120, pp. 53--58, August 1998.
大会等発表論文
[1]  山崎 聖一, 密山 幸男, 尾上 孝雄, ``文字重心位置を利用した文字ストローク自動補正手法の検討,'' 電子情報通信学会 2007ソサイエティ大会, A-20-13, September 2007.
[2]  濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``低電圧回路向け基板電位制御レイアウト方式の面積効率評価,'' 電子情報通信学会総合大会, A-3-6, March 2007.
[3]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``加算器を用いたsubthreshold 回路の設計指針の検討,'' 電子情報通信学会総合大会, A-3-17, March 2007.
[4]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``無線 LAN セキュリティ拡張規格向け暗号処理器のアーキテクチャ,'' 電子情報通信学会ソサイエティ大会, A-4-4, September 2003.
[5]  密山 幸男, 岩永 信之, 尾上 孝雄, 白川 功, ``Bluetooth スキャッタネットの構築手法と経路制御,'' 信学会 総合大会, A-4-68, March 2001.
[6]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いた暗号方式,'' 信学会 ソサイエティ大会, A-4-42, October 2000.

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