論文誌
[1]  M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1853-1860, October 1997.
国際会議
[1]  M.Yamaguchi, T. Nakaoka, A. Yamada, and T. Kambe, ``An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1584-1587, June 1997.
[2]  M. Yamaguchi, A. Yamada, T. Nakaoka, and T. Kambe, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pp. 503-508, January 1997.
研究会等発表論文
[1]  山口雅之, 中岡敏博, 神戸尚志, ``データパス構成と並列制約にもとづくアーキテクチャ評価システム,'' 電子情報通信学会技術研究報告, VLD96-74, CPSY96-86, pp. 71-78, December 1996.
大会等発表論文
[1]  中岡敏博, 山口雅之, 山田晃久, 神戸尚志, ``評価システムを用いたプログ ラム方式専用プロセッサの設計支援,'' 情報処理学会 第53回全国大会, 2B-1, pp. 21-22, September 1996.

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