論文誌
[1]  M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of LCD Driver Circuit for Technology Migration,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2712--2717, December 2007.
[2]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538--3545, December 2006.
[3]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538-3545, December 2006.
[4]  内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, ``グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積りの容易化,'' 情報処理学会論文誌, vol. 47, no. 6, pp. 1665--1673, June 2006.
[5]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線容量抽出手法,'' 情報処理学会論文誌, vol. 46, no. 6, pp. 1395--1403, June 2005.
[6]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays,'' IEICE Trans. on Fundamentals, vol. E86-A, no. 12, pp. 2923--2932, December 2003.
国際会議
[1]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays,'' In In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.
[2]  T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of Lcd Driver Circuit for Technology Migration,'' In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), vol. 1, p. I25--I28, July 2006.
[3]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, November 2005.
[4]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix Lcd,'' In A Design Scheme for Sampling Switch in Active Matrix LCD, August 2005.
[5]  Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, ``Interconnect Capacitance Extraction for System LCD Circuits,'' In in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005), pp. 160--163, April 2005.
[6]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, 1C-03.3, 2005.
[7]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix LCD,'' In Proceedings of European Conference on Circuit Theory and Design, 3e-212, 2005.
[8]  Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for TFT Liquid Crystal Displays,'' In in Proc. The European Solid-State Device Research Conference (ESSDERC2003) , Estoril, Portugul, pp. 453--456, September 2003.
[9]  Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for On-Chip Interconnects,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and ommunications (ITC-CSCC2003) , Kang-Woo Do, Korea, vol. 3, pp. 1638--1641, July 2003.
[10]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``A Parasitic Capacitance Modeling Method for Non-Planar Interconnects,'' In in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 294--299, April 2003.
[11]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Multilevel Interconnects,'' In in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002, vol. 1, pp. 59--64, December 2002.
[12]  M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa, ``Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 589--592, September 2001.
[13]  G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura, ``Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pp. 949-954, November 1996.
[14]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 351-354, May 1996.
[15]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``A VLSI Architecture of MPEG2 MP@{hl} Motion Estimator,'' In in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 664-667, May 1996.
[16]  M. Furuie, T. Onoye, S. Tsukiyama, and Isao Shirakawa, ``Two-Dimensional Array Layout for Low Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Conference on Electronics Packaging(2001 ICEP), Tokyo, April, 2001., pp. 417--421, .
研究会等発表論文
[1]  伊地知孝仁, 橋本昌宜, 高橋真吾, 築山修治, 白川功, ``画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術,'' 信学技報, VLD2005-131, pp. 55--60, March 2006.
[2]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線間容量抽出手法,'' 信学技報, VLD2004-64, pp. 19--24, December 2004.
[3]  内田 好弘, 谷 貞宏, 築山 修治, 白川 功, ``領域分割による配線間容量モデル化手法について,'' 信学技報, NLP2003-21, pp. 7--12, June 2003.
[4]  谷 貞宏, 内田 好弘, 築山 修治, 白川 功, ``配線間容量モデル化とその評価について,'' 信学技報 DSP2002-83, pp. 7--12, June 2002.
大会等発表論文
[1]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶に適した配線間容量抽出の検討,'' 電子情報通信学会ソサイエティ大会, A-1-16, September 2004.

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