論文誌
[1]  S. Kimura, M. Hashimoto, and T. Onoye, ``A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2292--2300, December 2012.
[2]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp. 899-906, April 2005.
[3]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``Implementation of Java Accelerator for High-Performance Embedded Systems,'' in IEICE Trans. Fundamentals, vol. E86-A, no. 12, pp. 3079--3088, December 2003.
[4]  木村 浩三, 奥畑 宏之, 尾上 孝雄, 白川 功, 清原 督三, 鷺島 敬之, ``マルチスレッドプロセッサのデータキャッシュ制御方式,'' 映像情報メディア学会誌, vol. 52, no. 5, pp. 742--749, May 1998.
国際会議
[1]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 283--289, February 2012.
[2]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 46--51, April 2011.
[3]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Embedded Architecture of IEEE802.11i Cipher Algorithms,'' In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pp. 241--246, September 2004.
[4]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``A Java Accelerator for High Performance Embedded Systems,'' In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.
[5]  M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, ``High Performance Java Hardware Engine and Software Kernel for Embedded Systems,'' In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pp. 365--369, December 2001.
[6]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``High Performance Java Execution for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 346--350, October 2001.
研究会等発表論文
[1]  榎並 孝司, 木村 修太, 橋本 昌宜, 尾上 孝雄, ``自己性能補償に向けたカナリアFF挿入手法,'' 情報処理学会DAシンポジウム, pp. 227-232, September 2010.
[2]  ワットカナッド・ウィラポーン, 木村基, 藤田玄, 尾上孝雄, 白川功, ``動画像マルチデコーダ用動き補償機構のVLSIアーキテクチャ,'' 信学技報, SIS2004-62, pp. 37--43, March 2005.
[3]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``組込みシステム向け IEEE802.11i 暗号処理回路の実装,'' 信学技報, ICD2004-129, pp. 49--54, October 2004.
[4]  木村基, 密山幸男, 尾上孝雄, 白川功, ``組込みシステム向け IEEE 802.11i 暗号処理器のアーキテクチャ,'' 第17回回路とシステム軽井沢ワークショップ, pp. 217--222, April 2004.
[5]  木村 基, 三木 裕介, 尾上 孝雄, 白川 功, ``組込みシステム向け Java 実行環境の構築,'' 信学技報, VLD2001-137, pp. 39--44, January 2002.
大会等発表論文
[1]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``無線 LAN セキュリティ拡張規格向け暗号処理器のアーキテクチャ,'' 電子情報通信学会ソサイエティ大会, A-4-4, September 2003.

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