論文誌
[1]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3461-3464, December 2008.
[2]  K. Kawamoto, H. Yamaguchi, H. Himi, S. Fujino, and I. Shirakawa, ``A 200 V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays,'' IEICE Trans. Electron, vol. E84-C, no. 2, pp. 260--266, February 2001.
[3]  Masayuki Yamaguchi, Nagisa Ishiura, and Takashi Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal DSP Architecture,'' IEICE Trans. Fundamentals, vol. E81-A, no. 12, pp. 2630--2639, December 1998.
[4]  M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1853-1860, October 1997.
国際会議
[1]  Takashi Nakamae, Akihisa Yamada, Masayuki Yamaguchi, and Takao Onoye, ``A Near-Lossless Image Compression Method Using Adaptive Variable Length Coding,'' In International Conference on Embedded Systems and Intelligent Technology, January 2012.
[2]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' In Proc. IEEE European Solid-State Device Research Conference, pp. 115-118, September 2007.
[3]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``SoC Design of Ogg Vorbis Decoder Using Embedded Processor,'' In in Proc. 2004 Computing Frontier Conference, pp. 481--487, April 2004.
[4]  S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low Power Ogg Vorbis Decoder by Embedded Processor,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 1, pp. 565--568, July 2003.
[5]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications,'' In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pp. 20--24, September 2002.
[6]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor,'' In in Proc. 17th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), Phuket, Thailand, pp. 94--97, July 2002.
[7]  N. Ishiura, T. Watanabe, and M. Yamaguchi, ``A Code Generation Method for Datapath Oriented Application Specific Processor Design,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pp. 71--78, April 2000.
[8]  N. Ishiura and M. Yamaguchi, ``Operation Binding for Retargetable Compilers Minimizing Clock Cycles,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 705--708, July 1999.
[9]  N. Ishiura, M. Yamaguchi, and T. Kambe, ``A Graph-Based Algorithm of Operation Binding for Compilers Targeting Heterogeneous Datapath,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 395--398, November 1998.
[10]  M. Yamaguchi, N. Ishiura, and T. Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal Datapath Architectures,'' In in Proc. International Symposium on Circuits and Systems, WPA4-4, June 1998.
[11]  M. Yamaguchi, N. Ishiura, and T. Kambe, ``Binding and Scheduling Algorithms for Highly Retargetable Compilation,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 93-98, February 1998.
[12]  N. Ishiura and M. Yamaguchi, ``Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning,'' In in Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), pp. 105-109, December 1997.
[13]  M.Yamaguchi, T. Nakaoka, A. Yamada, and T. Kambe, ``An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1584-1587, June 1997.
[14]  M. Yamaguchi, A. Yamada, T. Nakaoka, and T. Kambe, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pp. 503-508, January 1997.
研究会等発表論文
[1]  中前貴司, 山田晃久, 山口雅之, 尾上孝雄, ``フレームメモリ容量削減のための準可逆画像圧縮手法,'' 信学技報, CAS2011-29, vol. 111, no. 102, pp. 163-168, June 2011.
[2]  小坂篤史, 山口悟史, 奥畑宏之, 尾上孝雄, 白川功, ``組み込みCPUと専用回路によるOgg Vorbis音楽デコーダのVLSI化設計,'' 信学技報, SDM2002-159, ICD2002-70, pp. 37--42, August 2002.
[3]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``特定用途向け DSP のデータパス指向協調設計におけるコード生成手法,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 539--544, April 2000.
[4]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``非直交なデータパスに対するリターゲッタブルコンパイラのスケジューリング手法,'' 信学会 第12回回路とシステム軽井沢ワークショップ, pp. 109--114, April 1999.
[5]  服部 靖史, 石浦 菜岐佐, 山口 雅之, ``DSP向けリターゲッタブルコンパイラの演算器/転送経路のバインディング手法,'' 信学技報, VLD98-125, vol. 98, no. 447, pp. 55-61, December 1998.
[6]  山口雅之, 石浦菜岐佐, 神戸尚志, ``非直交なデータパスに対するリターゲッタブルコンパイラのバインディング手法,'' 信学会 第11回回路とシステム軽井沢ワークショップ, pp. 481--486, April 1998.
[7]  山口雅之, 石浦菜岐佐, 神戸尚志, ``組込み式システム向けリターゲッタブルコンパイラの方式,'' 電子情報通信学会技術研究報告, VLD97-90, FTS97-53, pp. 85-92, October 1997.
[8]  山本哲三朗, 石浦菜岐佐, 山口雅之, 服部靖史, ``組込みシステム向け高位合成システム,'' 電子情報通信学会技術研究報告, VLD97-91, FTS97-54, pp. 93-99, October 1997.
[9]  山口雅之, 中岡敏博, 神戸尚志, ``データパス構成と並列制約にもとづくアーキテクチャ評価システム,'' 電子情報通信学会技術研究報告, VLD96-74, CPSY96-86, pp. 71-78, December 1996.
大会等発表論文
[1]  前田真一, 山口悟史, 小坂篤史, 奥畑宏之, 山田晃久, 尾上孝雄, 白川功, ``Bach C言語によるOgg VorbisデコーダのVLSI化設計,'' 信学会 総合大会, A-3-8, March 2003.
[2]  山口 悟史, 小坂 篤史, 奥畑 宏之, 白川 功, ``組み込み CPU 向け Ogg Vorbis デコーダの VLSI 実装,'' 信学会 総合大会, A-3-8, March 2001.
[3]  石浦菜岐佐, 山口雅之, ``特定用途向けVLIW型プロセッサの命令コード圧縮手法,'' 電子情報通信学会ソサイエィ大会, A-3-10, August 1997.
[4]  中岡敏博, 山口雅之, 山田晃久, 神戸尚志, ``評価システムを用いたプログ ラム方式専用プロセッサの設計支援,'' 情報処理学会 第53回全国大会, 2B-1, pp. 21-22, September 1996.

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