論文誌
[1]  密山 幸男, 高橋 一真, 今井 林太郎, 橋本 昌宜, 尾上 孝雄, 白川 功, ``メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現,'' 電子情報通信学会論文誌, vol. J93-A, no. 6, pp. 397-413, June 2010.
[2]  Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa, ``Area-Efficient Reconfigurable Architecture for Media Processin,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3651-3662, December 2008.
[3]  M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of LCD Driver Circuit for Technology Migration,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2712--2717, December 2007.
[4]  M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, ``Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4,'' International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.
[5]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538--3545, December 2006.
[6]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538-3545, December 2006.
[7]  内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, ``グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積りの容易化,'' 情報処理学会論文誌, vol. 47, no. 6, pp. 1665--1673, June 2006.
[8]  G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa, ``Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation,'' In IEICE Trans. Fundamentals, vol. E89-A, no. 4, pp. 941--949, April 2006.
[9]  Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network,'' IEEE Transactions on Consumer Electronics, vol. 52, no. 1, pp. 81--86, February 2006.
[10]  M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``W-CDMA Channel Codec by Configurable Processors,'' In Intelligent Automation and Soft Computing, vol. 12, no. 3, pp. 317--29, 2006.
[11]  藤田玄, 尾上孝雄, 白川功, ``MPEG-4向け高精度動き検出コアのVLSI化設計,'' 電子情報通信学会論文誌, vol. J88-A, no. 11, pp. 1282-1382, November 2005.
[12]  A. Kosaka, H. Okuhata, T. Onoye, and I. Shirawaka, ``Desing of Ogg Vorbis Decoder System for Embedded Platform,'' IEICE Trans. Fundamentals, vol. E88-A, no. 8, pp. 2124--2130, August 2005.
[13]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線容量抽出手法,'' 情報処理学会論文誌, vol. 46, no. 6, pp. 1395--1403, June 2005.
[14]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 4, pp. 899-906, April 2005.
[15]  T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function,'' IEEE Transactions on Consumer Electronics, vol. 51, no. 1, pp. 262--267, February 2005.
[16]  岡田 勉, 内田 翼, 尾上 孝雄, 白川 功, ``次世代 GNSS 受信機用信号処理 機構とその VLSI 化設計,'' 電子情報通信学会論文誌, vol. J86-A, no. 12, pp. 1417--1425, December 2003.
[17]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays,'' IEICE Trans. on Fundamentals, vol. E86-A, no. 12, pp. 2923--2932, December 2003.
[18]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``Implementation of Java Accelerator for High-Performance Embedded Systems,'' in IEICE Trans. Fundamentals, vol. E86-A, no. 12, pp. 3079--3088, December 2003.
[19]  宋 学燮, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4動画像符号化におけるバイブリッドエラー隠ぺい方式,'' 画像電子学 会論文誌, vol. 32, no. 5, pp. 609--620, September 2003.
[20]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources,'' in IEEE Trans. on Consumer Electronics, vol. 49, no. 3, pp. 737--741, August 2003.
[21]  K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa, ``Object Sharing Scheme for Heterogeneous Environment,'' in IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 4, pp. 813--821, April 2003.
[22]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm,'' Journal of Circuits, Systems and Computers, vol. 12, no. 1, pp. 55-73, February 2003.
[23]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Performance Estimation at Architecture Level for Embedded Systems,'' IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 12, pp. 2636--2644, December 2002.
[24]  Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, ``Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Communications, vol. E85-B, no. 10, pp. 2032--2043, October 2002.
[25]  岡田 浩行, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``電子透かしのMPEG-4ビットストリームエラー検出への応用,'' 画像電子学会誌, vol. 31, no. 5, pp. 900--908, September 2002.
[26]  H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Detection by Digital Watermarking for MPEG-4 Video Coding,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 6, pp. 1281--1288, June 2002.
[27]  宋 天, 藤田 玄, 尾上 孝雄, 白川 功, ``携帯端末用低消費電力 H.263 Version 2 コーデックコアのVLSI化設計,'' 情報処理学会論文誌, vol. 43, no. 4, pp. 1161--1170, May 2002.
[28]  M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, ``Code Efficiency Evaluation for Embedded Processors,'' IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 4, pp. 811--818, April 2002.
[29]  Roberto Y. Omaki, Gen Fujita, Takao Onoye, and Isao Shirakawa, ``An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E85-A, no. 3, pp. 703--713, March 2002.
[30]  谷 貞宏, 白川 功, ``多層プリント回路板の電源供給系におけるインピーダンスシミュレーション,'' エレクトロニクス実装学会誌, vol. 4, no. 5, pp. 378--385, August 2001.
[31]  W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' IEICE(The Institute of Electronics, Information and Communication Engineers) Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1423--1430, June 2001.
[32]  K. Kawamoto, K. Kohno, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A 25kV ESD Proof LDMOSFET with a Turn-On Discharge MOSFET,'' IEICE Trans. Electron, vol. E84-C, no. 6, pp. 823--831, June 2001.
[33]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A Novel Dynamically Reconfigurable Hardware-Based Cipher,'' 情報処理学会論文誌, vol. 42, no. 4, pp. 958--966, April 2001.
[34]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, ``A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS,'' The Japan Society of Applied Physics, vol. 40, no. 4B, pp. 2891--2896, April 2001.
[35]  K. Kawamoto, H. Yamaguchi, H. Himi, S. Fujino, and I. Shirakawa, ``A 200 V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays,'' IEICE Trans. Electron, vol. E84-C, no. 2, pp. 260--266, February 2001.
[36]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic,'' Trans. of IPSJ, vol. 41, no. 4, pp. 899--907, April 2000.
[37]  松村 謙次, 古家 眞, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘, ``医療用監視システムとその通信制御用 LSI の設計,'' 情報処理学会論文誌, vol. 41, no. 4, pp. 962--969, April 2000.
[38]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Scheme of NMOS 4-Phase Dynamic Logic,'' IEICE Trans. Electron., vol. E82--C, no. 9, pp. 1772--1776, September 1999.
[39]  H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``An Architecture of a Matrix-Vector Multiplier Dedicated to Video Decoding and Three-Dimensional Computer Graphics,'' IEEE Trans. Circuits and Systems for Video Technology, vol. 9, no. 2, pp. 306--314, March 1999.
[40]  A. Nagao, I. Shirakawa, and T. Kambe, ``A Layout Approach to Monolithic Microwave IC,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1262--1272, December 1998.
[41]  M. H. Miki, 藤田 玄, 尾上 孝雄, 白川 功, ``携帯端末向け低電力 H.263 コーデックコアの VLSI 化設計,'' 電子情報通信学会論文誌, vol. J81-A, no. 10, pp. 1352--1361, October 1998.
[42]  長尾 明, 澤 卓, 重弘 裕二, 白川 功, 神戸 尚志, ``方形パッキング法の一算法,'' 電子情報通信学会論文誌, vol. J81-A, no. 10, pp. 1362--1371, October 1998.
[43]  H. Okuhata, Morgan H. Miki, T. Onoye, and I. Shirakawa, ``A Low-Power DSP Core Architecture for Low Bitrate Speech Codec,'' IEICE Trans. Fundamentals, vol. E81-C, no. 8, pp. 1616--1621, August 1998.
[44]  木村 浩三, 奥畑 宏之, 尾上 孝雄, 白川 功, 清原 督三, 鷺島 敬之, ``マルチスレッドプロセッサのデータキャッシュ制御方式,'' 映像情報メディア学会誌, vol. 52, no. 5, pp. 742--749, May 1998.
[45]  G. Fujita, T. Onoye, and I. Shirakawa, ``A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding,'' IEICE Trans. Electronics, vol. E81-C, no. 5, pp. 702--707, May 1998.
[46]  I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 12, pp. 2589-2599, December 1997.
[47]  吉田 幸弘, 宋 宝玉, 奥畑 宏之, 尾上 孝雄, 白川 功, ``組み込み用プロセッサの低消費電力化に関する一手法,'' 電子情報通信学会論文誌, vol. J80-A, no. 5, pp. 765-771, May 1997.
[48]  K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication,'' J. Circuits, Systems, and Computers, vol. 7, no. 5, pp. 441-457, May 1997.
[49]  H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, ``A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication,'' J. Circuits, Systems, and Computers, vol. 7, no. 5, pp. 483-494, May 1997.
[50]  H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, ``ASK Digital Demodulation Scheme for Noise Immune Infrared Data Communication,'' ACM Wireless Networks, no. 3, pp. 121-129, 1997.
[51]  K. Okada, S. Morikawa, S. Takeuchi, and I. Shirakawa, ``A High Performance Multiplier and Its Application to an FIR Filter Dedicated to Digital Video Transmission,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E79-A, no. 12, pp. 2106-2111, December 1996.
[52]  Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``Automatic Layout Recycling Based on Layout Description and Linear Programming,'' in Proc. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp. 959-967, August 1996.
[53]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai, ``Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@{hl},'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E79-A, no. 8, pp. 1210-1216, August 1996.
国際会議
[1]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays,'' In In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.
[2]  H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa, ``Video Image Enhancement Scheme for High Resolution Consumer Devices,'' In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP2008), pp. 639-644, March 2008.
[3]  T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of Lcd Driver Circuit for Technology Migration,'' In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), vol. 1, p. I25--I28, July 2006.
[4]  Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``Domain-Specific Reconfigurable Architecture for Media Processing,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2006), pp. 322--327, April 2006.
[5]  Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network,'' In International Conference on Consumer Electronics(ICCE2006), digest of technical papers, Las Vegas, Nevada, USA, pp. 391--392, January 2006.
[6]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, November 2005.
[7]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix Lcd,'' In A Design Scheme for Sampling Switch in Active Matrix LCD, August 2005.
[8]  Huynh Van Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Real-Time Human Object Extraction for Mobile Terminal,'' In in Proc.The 20th Commemorative International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005), Jeju, Korea, vol. 3, pp. 1015-1016, July 2005.
[9]  Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, ``An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing,'' In Proc. International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC2005), pp. 131--132, July 2005.
[10]  T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai, ``3D Sound Movement System for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2005), Kobe, Japan, pp. 5345-5348, May 2005.
[11]  Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, ``Interconnect Capacitance Extraction for System LCD Circuits,'' In in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005), pp. 160--163, April 2005.
[12]  T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function,'' In in Proc.~International Conference on Consumer Electronics (ICCE2005), digest of technical papers, Las Vegas, Nevada, USA, 7.1-2, January 2005.
[13]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, 1C-03.3, 2005.
[14]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix LCD,'' In Proceedings of European Conference on Circuit Theory and Design, 3e-212, 2005.
[15]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``VLSI Implementation of 3D Sound Image Movement for Embedded Systems,'' In in Proc. IEEE Region 10 Conference (TENCON) 2004, A--021, November 2004.
[16]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a 3D Sound Movement System,'' In in Proc. The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2004, pp. 121-125, October 2004.
[17]  Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, ``Embedded Architecture of IEEE802.11i Cipher Algorithms,'' In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pp. 241--246, September 2004.
[18]  S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa, ``C-Based Hardware Design of IMDCT Accelerator for Ogg Vorbis Decoder,'' In in Proc.12th European Signal Processing Conference (EUSIPCO 2004), pp. 1361--1364, September 2004.
[19]  Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa, ``Architecture of Turbo Decoder for W-CDMA by Configurable Processor,'' In Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4, p. 7, July 2004.
[20]  T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, ``Embedded System Implementation of Scalable and Object-Based Video Coding,'' In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.
[21]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``SoC Design of Ogg Vorbis Decoder Using Embedded Processor,'' In in Proc. 2004 Computing Frontier Conference, pp. 481--487, April 2004.
[22]  K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Modified Snake: Real-Time Face Object Extraction for Video Phone,'' In in Proc. IEEE International Conference on Image Processing(ICIP2003), Barcelona, Spain, vol. III, pp. 873--876, September 2003.
[23]  M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``Implementation of W-CDMA Channel Codec by Configurable Processors,'' In Proc. Sixth Baiona Workshop on Signal Processing in Communications, pp. 205--210, September 2003.
[24]  Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for TFT Liquid Crystal Displays,'' In in Proc. The European Solid-State Device Research Conference (ESSDERC2003) , Estoril, Portugul, pp. 453--456, September 2003.
[25]  H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Efficient Error Recovery Scheme for MPEG-4 Video Coding,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 2, pp. 1328--1331, July 2003.
[26]  Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, ``Parasitic Capacitance Modeling for On-Chip Interconnects,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and ommunications (ITC-CSCC2003) , Kang-Woo Do, Korea, vol. 3, pp. 1638--1641, July 2003.
[27]  S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low Power Ogg Vorbis Decoder by Embedded Processor,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 1, pp. 565--568, July 2003.
[28]  T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Feature Extraction of Head-Related Transfer Function for 3D Sound Movement,'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, vol. 1, pp. 685--688, July 2003.
[29]  N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources,'' In in IEEE 29th International Conference on Consumer Electronics (ICCE2003), digest of technical papers, Los Angeles, Carifornia, USA, pp. 256--257, June 2003.
[30]  T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, ``A Novel Signal Processing Scheme for Next Generation GNSS Receiver,'' In in Proc. the 8th ISU International Symposium, Strasbourg, France, May 2003.
[31]  S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Interactive Interface of Realtime 3D Sound Movement for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, vol. II, pp. 520--523, May 2003.
[32]  T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, ``A Novel Signal Processing Scheme for Next Generation GNSS Receiver and Its VLSI Implementation,'' In in Proc. International Signal Processing Conference , Dallas, no. 357, April 2003.
[33]  N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I.Shirakawa, ``Low Cost Approach to Acoustic Field Enhancement for Stereo Headphones,'' In in Proc. Euromedia 2003, Plymouth, United Kingdom, pp. 32--36, April 2003.
[34]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``A Parasitic Capacitance Modeling Method for Non-Planar Interconnects,'' In in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 294--299, April 2003.
[35]  T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa, ``Vlsi Architecture for Mpeg-4 Core Profile Codec Core,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 365--371, April 2003.
[36]  K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, ``Realtime Face Object Extraction Algorithm for Video Phone,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), Orchard Road, Singapore, vol. 1, pp. 35--38, December 2002.
[37]  Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, ``Implementation of Wireless MPEG2 Transmission System Using IEEE 802.11b PHY,'' In ibid, vol. 1, pp. 39--44, December 2002.
[38]  N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, ``Embedded Implementation of Acousitic Field Enhancement for Stereo Headphones,'' In ibid, vol. 1, pp. 51--54, December 2002.
[39]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Multilevel Interconnects,'' In in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002, vol. 1, pp. 59--64, December 2002.
[40]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications,'' In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pp. 20--24, September 2002.
[41]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor,'' In in Proc. 17th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), Phuket, Thailand, pp. 94--97, July 2002.
[42]  S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Synthesis of 3D Sound Movement by Embedded DSP,'' In ibid, pp. 117--120, July 2002.
[43]  H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Digital Watermark Based Error Detection for MPEG-4 Bitstream Error,'' In ibid, pp. 152--155, July 2002.
[44]  T. Kaya, R. Miyamoto, T. Onoye, and I. Shirakawa, ``Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Processor,'' In ibid, pp. 216--219, July 2002.
[45]  H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Hybrid Error Concealment Algorithm for MPEG-4 Videodecoders,'' In ibid, pp. 611--614, July 2002.
[46]  K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, O. Tsumori, K. Hanada, T. Chiba, and I. Shirakawa, ``OCEAN: Object Communication Environment for Arbitrary Network,'' In in Proc. IEEE International Conference on Distributed Computing Systems Workshops, pp. 162--166, July 2002.
[47]  W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, ```Out-Of-Head' Acoustic Field Enhancement for Stereo Headphones by Embedded DSP,'' In in IEEE 28th International Conference on Consumer Electronics (ICCE2002), digest of technical papers, Cardiff, Wales, pp. 222--223, June 2002.
[48]  Y. Ohtani, N. Kawahara, T. Onoye, I. Shirakawa, and T. Chiba, ``MAC LSI Design for Wireless MPEG2 Transmission Over IEEE802.11b PHY,'' In ibid, pp. 242--243, June 2002.
[49]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``Burst Mode: a New Acceleration Mode for 128-Bit Block Ciphers,'' In in Proc. IEEE 24th Custom Integrated Circuits Conference (CICC2002), Orland, Florida, pp. 151--154, May 2002.
[50]  Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Digital Matched Filter and Prime Interleaver for W-CDMA,'' In Proc. IEEE International Symposium on Circuits and Systems (ISCAS2002), Phoenix, Arizona, vol. III, pp. 269--272, May 2002.
[51]  Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers,'' In ibid, vol. II, pp. 344--347, May 2002.
[52]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Power Estimation at Architecture Level for Embedded Systems,'' In ibid, vol. II, pp. 476--479, May 2002.
[53]  Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, and T. Chiba, ``Error Correction Block Based ARQ Protocol for Wireless Digital Video Transmission,'' In ibid, vol. I, pp. 605--608, May 2002.
[54]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``A Java Accelerator for High Performance Embedded Systems,'' In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.
[55]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Synthesis Algorithm for Monaural Sound Source,'' In in Proc. EUROMEDIA 2002, Modena, Italy, pp. 123--127, April 2002.
[56]  M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, ``High Performance Java Hardware Engine and Software Kernel for Embedded Systems,'' In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pp. 365--369, December 2001.
[57]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``An Architecture Level Power Estimation Method for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 78--85, October 2001.
[58]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``System Performance Evaluation of High-Speed Burst Mode for 128-Bit Block Ciphers,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 332--339, October 2001.
[59]  M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, ``High Performance Java Execution for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 346--350, October 2001.
[60]  M. Ise, Y. Uchida, T. Onoye, and I. Shirakawa, ``System-On-A-Chip Architecture for W-CDMA Baseband Modem LSI,'' In in Proc. The 4th International Conference on ASIC (ASICON 2001), Shanghai, pp. 364--369, October 2001.
[61]  M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa, ``Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 589--592, September 2001.
[62]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementaion of 3D Sound Localization Algorithm for Monaural Sound Source,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 1061--1064, September 2001.
[63]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Low Computational 3D Sound Localization Algorithm,'' In in Proc. 200l IEEE Workshop on Signal Processing Systems, Design and Implementation(SIPS 2001), Antwerp, Belgium, pp. 109--116, September 2001.
[64]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers,'' In in Proc. 14th Annual IEEE International ASIC/SoC Conference (ASIC/SoC2001), Washington, D.C., pp. W.1.1.1--W.1.1.5, September 2001.
[65]  H. Okada, H. S. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Detection Based on Check Marker Embedding for MPEG-4 Video Coding,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 96--99, July 2001.
[66]  H. S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, ``Error Concealment Algorithm by Motion Estimation Method for MPEG-4 Video Decoder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 104--107, July 2001.
[67]  T. Song, G. Fujita, T. Onoye, and I. Shirakawa, ``Low Power Architecture for H.263 Version2 Codec,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 620--623, July 2001.
[68]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Localization Algorithm,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 1140--1143, July 2001.
[69]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization for Monaural Sound Source,'' In in Proc. World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001), Orlando, Florida, USA, pp. 173--177, July 2001.
[70]  M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, ``Evaluation of Processor Code Efficiency for Embedded Systems,'' In in Proc. ACM 15th International Conference on Supercomputing, Sorrento, Italy, pp. 229--235, June 2001.
[71]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, vol. IV, pp. 734--737, May 2001.
[72]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A High Performance Burst Mode Approach for 128-Bit Block Ciphers,'' In in Proc. EUROMEDIA2001, Valencia, Spain, pp. 146--150, April 2001.
[73]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A Dynamically Reconfigurable Hardware-Based Cipher Chip,'' In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 11--12, January 2001.
[74]  R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``Realtime Wavelet Video Coder Based on Reduced Memory Accessing,'' In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 15--16, January 2001.
[75]  S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Portable MPEG-4 Audio Decoder,'' In in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA, pp. 80--84, September 2000.
[76]  Y. Dong, R. Y. Omaki, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder,'' In in Proc. International Conference on Image Processing (ICIP 2000), vol. III, pp. 126--129, September 2000.
[77]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A Shingle Chip Automotive Control LSI Using SOI BiCDMOS,'' In in Proc. of 2000 International Conference on Solid State Device and Materials, pp. 486-487, August 2000.
[78]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 253--256, July 2000.
[79]  W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 264--267, July 2000.
[80]  R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa, ``Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 811--814, July 2000.
[81]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Symposium on VLSI Circuits Digest of Technical Papers, Hawaii, USA, pp. 204--205, June 2000.
[82]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``Chameleon: a Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pp. 90--94, May 2000.
[83]  R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a Realtime Wavelet Video Coder,'' In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pp. 543--546, May 2000.
[84]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic,'' In in Proc. ASP-DAC2000, pp. 529--532, January 2000.
[85]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Video Coding Algorithm Based on Modified Discrete Wavelet Transform,'' In in Proc. NOLTA'99, vol. I, pp. 251--254, November 1999.
[86]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Architecture of Embedded Zerotree Wavelet Based Real-Time Video Coder,'' In in Proc. 12th IEEE ASIC/SOC Conference, pp. 137-141, October 1999.
[87]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Embedded Zerotree Wavelet Based Algorithm for Video Compression,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp.II-1343--1346, September 1999.
[88]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 872--875, September 1999.
[89]  M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa, ``High-Speed Implementation of JBIG Arithmetic Coder,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 1291--1294, September 1999.
[90]  B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 561--564, July 1999.
[91]  M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa, ``Pipelined Implementation of JBIG Arithmetic Coder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 470--473, July 1999.
[92]  M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, ``Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, vol. IV, pp. 572--575, June 1999.
[93]  H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, ``Hybrid Media-Processor Core for Natural and Synthetic Video Decoding,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, vol. IV, pp. 275--278, June 1999.
[94]  G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``Low-Power Architecture of H.324 Codec Dedicated to Mobile Computing,'' In in Proc. EUROMEDIA'99 , Munich, Germany, pp. 145--149, April 1999.
[95]  K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, ``Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware,'' In in Proc. IEEE Internatinal Solid-State Circuits Conference, pp. 106--107, February 1999.
[96]  H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, ``Hybrid VLSI Architecture for Motion Compensation and Texture Mapping,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 383--386, November 1998.
[97]  J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, ``Structual Objeco-Oriented Video Segmentation and Representation Algorithm,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 78--82, November 1998.
[98]  H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura, ``Matrix-Vector Multiplier Module for Natural/Synthetic Hybrid Video Coding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 631--634, November 1998.
[99]  B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Implementation by a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 235--240, October 1998.
[100]  B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Delay and Power Simulation for a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. European Simulation Symposium, pp. 339--343, October 1998.
[101]  J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, ``Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding,'' In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pp. 141--151, September 1998.
[102]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System Constructed of SAW-Based Receiver/Transmitter and Its Applications to Medical Cares,'' In in Proc. IEEE Radio & Wireless Conf., pp. 47--50, August 1998.
[103]  Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Function Module for Texture Mapping and Motion Compensation,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 179--182, July 1998.
[104]  R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, ``Implementation of DWT and EZW Cores for a Bitrate Scalable Video Coder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 221--224, July 1998.
[105]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System by Means of SAW-Based Transmitter/Receiver and Its Applications to Medical Cares,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 299--302, July 1998.
[106]  H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``Matrix-Vector Multiplier for Natural/Synthetic Hybrid Video Coding,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1269--1272, July 1998.
[107]  D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, ``VLSI Implementation of a Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1383--1386, July 1998.
[108]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data Systems Constructed of SAW-Divices and Its Applications to Medical Cares,'' In in Proc. Analog VLSI WS, pp. 39--44, June 1998.
[109]  G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``Implementation of H.324 Audiovisual Codec for Mobile Computing,'' In in Proc.\ IEEE Custom Integrated Circuits Conference, pp. 193--196, May 1998.
[110]  H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, ``A Low Power DSP Core Architecture for Low Bitrate Speech Codec,'' In in Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal Processing, pp. 3121--3124, May 1998.
[111]  T. Onoye, G. Fujita, H. Okuhata, M. H. Miki, and I. Shirakawa, ``Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 589-594, February 1998.
[112]  H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi, ``A Unified Media-Processor Architecure for Video Coding and Computer Graphics,'' In in Proc. International Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional Imaging, pp. 253-256, September 1997.
[113]  M. H. Miki, G.Fujita, T. Onoye, and I. Sirakawa, ``Low-Power H.263 Video CoDec Dedicated to Mobile Computing,'' In in Proc. International Symposium on Low Power Electronics and Design, pp. 80-83, August 1997.
[114]  H. Uno, K. Kumatani, H. Okuhata, T. Chiba, and I. Shirakawa, ``Low Power Architecture for High Speed Infrared Wireless Communication System,'' In in Proc.International Symposium on Low Power Electronics and Design, pp. 255-258, August 1997.
[115]  Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``An Object Code Compression Approach to Embedded Processors,'' In in Proc. International Symposium on Low Power Electronics and Design, pp. 265-268, August 1997.
[116]  H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``Media-Processor Architecture Unified for Video Coding and 3D Graphics,'' In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pp. 1223-1226, July 1997.
[117]  G. Fujita, T. Onoye, and I. Sirakawa, ``A New Motion Estimation Core Dedicated to H.263 VideoCoding,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1161-1164, June 1997.
[118]  I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimun Cost Flow Algofithm for VLSI Layout Compaction,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1672-1675, June 1997.
[119]  K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication,'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 229-232, May 1997.
[120]  H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Link Dedicated to Mobile Computing,'' In in Proc. IEEE International Performance, Computing, and Communications Conference, pp. 463-467, February 1997.
[121]  S. Morikawa, K. Okada, S. Takeuchi, and I. Shirakawa, ``A High Performance FIR Filter Dedicated to Digital Video Transmission,'' In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pp. 77-82, January 1997.
[122]  G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura, ``Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pp. 949-954, November 1996.
[123]  H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Communication System Dedicated to Mobile Computing,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 334-337, November 1996.
[124]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 480-483, November 1996.
[125]  Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low-Power Consumption Architecture for Embedded Processor,'' In in Proc. 2nd International Conference on ASIC, pp. 77-80, October 1996.
[126]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``Implementation of Very Low Bitrate Video Encoder Core,'' In in Proc. 2nd International Conference on ASIC, pp. 131-134, October 1996.
[127]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura, ``A Single Chip Motion Estimator Dedicated to MPEG2 MP@{hl},'' In in Proc. European Signal Processing Conference, pp. 1479-1482, September 1996.
[128]  G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa, ``Single Chip MPEG2 MP@{ml} Motion Estimator,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 286-289, July 1996.
[129]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Architecture for Very Low Bitrate Video Encoder Core,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 294-297, July 1996.
[130]  S. Nakamura, N. Ishiura, T. Yamamoto, and I. Shirakawa, ``High-Level Synthesis System for Behavioral Descriptions with Conditional Branches,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 935-938, July 1996.
[131]  Y. Shigehiro, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm and Its Application to VLSI Layout Compaction,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 951-954, July 1996.
[132]  H. Uno, K. Kumatani, H. Okuhata, T. Masaki, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Communication Link for Mobile Computing,'' In in Proc. Workshop on Multi-Dimensional Mobile Communications (MDMC '96), pp. 267-271, July 1996.
[133]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@{hl},'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 351-354, May 1996.
[134]  T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, ``A VLSI Architecture of MPEG2 MP@{hl} Motion Estimator,'' In in Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 664-667, May 1996.
[135]  K. Itoh, Y. Shigehiro, I. Shirakawa, and K. Matsumura, ``An Approach for Multi-Layer Gridless Routing,'' In in Proc. Printed Circuit World Convention VII, pp.P2-1-P2-7, May 1996.
[136]  M. Furuie, T. Onoye, S. Tsukiyama, and Isao Shirakawa, ``Two-Dimensional Array Layout for Low Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Conference on Electronics Packaging(2001 ICEP), Tokyo, April, 2001., pp. 417--421, .
研究会等発表論文
[1]  伊勢正尚, 小笠原泰弘, 渡邊賢治, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``IEEE 802.15.4を用いたホームネットワーク向け無線ネットワークプロトコル,'' 信学技報, CAS2005-99, pp. 19--24, March 2006.
[2]  渡邊賢治, 伊勢正尚, 藤田玄, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``無線ホームネットワークにおける消費電力および即時性の改善手法,'' 信学技報, CAS2005-100, pp. 25--30, March 2006.
[3]  伊地知孝仁, 橋本昌宜, 高橋真吾, 築山修治, 白川功, ``画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術,'' 信学技報, VLD2005-131, pp. 55--60, March 2006.
[4]  藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4向け高精度動き検出コアのVLSI化設計,'' 電子情報通信学会, vol. J88-A, no. 11, pp. 1282--1291, November 2005.
[5]  野里 良裕, 奥畑 宏之, 尾上 孝雄, 白川 功, ``適応的階調補正のハードウェア実現における Retinex 理論の比較評価,'' 信学技報, SIS2005-16, pp. 19--24, June 2005.
[6]  藤田玄, 今仲隆晃, フィン ヴァン ニャット, 尾上孝雄, 白川功, ``色空間のブロック分割に基づく携帯端末向けリアルタイム人オブジェクト抽出手法,'' 第18回 回路とシステム軽井沢ワークショップ, pp. 431--436, April 2005.
[7]  ワットカナッド・ウィラポーン, 木村基, 藤田玄, 尾上孝雄, 白川功, ``動画像マルチデコーダ用動き補償機構のVLSIアーキテクチャ,'' 信学技報, SIS2004-62, pp. 37--43, March 2005.
[8]  郭朝暉, 西川裕規, 大巻 ロベルト 裕治, 尾上 孝雄, 白川 功, ``Motion JPEG2000 における誤り訂正符号の割当て手法,'' 信学技報, CAS2004-67, pp. 1--6, January 2005.
[9]  盧 承烈, 小笠原 泰弘, 伊勢 正尚, 畠中 理英, 尾上 孝雄, 庭本 浩明, 芥子 育雄, 白川 功, ``ユニバーサルプラグアンドプレイ技術を用いたホームネットワーク一構成方式,'' 信学技報, CAS2004-68, pp. 7--12, January 2005.
[10]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線間容量抽出手法,'' 信学技報, VLD2004-64, pp. 19--24, December 2004.
[11]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``組込みシステム向け IEEE802.11i 暗号処理回路の実装,'' 信学技報, ICD2004-129, pp. 49--54, October 2004.
[12]  今井 林太郎, 密山 幸男, 尾上 孝雄, 白川 功, ``メディア処理向けリコンフィギュラブルアーキテクチャに関する一検討,'' 電子情報通信学会 第4回リコンフィギャラブルシステム研究会, pp. 33--40, September 2004.
[13]  木村基, 密山幸男, 尾上孝雄, 白川功, ``組込みシステム向け IEEE 802.11i 暗号処理器のアーキテクチャ,'' 第17回回路とシステム軽井沢ワークショップ, pp. 217--222, April 2004.
[14]  中川陽介, 岩永信之, 小林亙, 古谷一彦, 尾上孝雄, 白川功, ``周波数特性除去に基づくスピーカによるバイノーラル再生,'' 聴覚研究会, pp. 17--22, January 2004.
[15]  内田 好弘, 谷 貞宏, 築山 修治, 白川 功, ``領域分割による配線間容量モデル化手法について,'' 信学技報, NLP2003-21, pp. 7--12, June 2003.
[16]  岩永信之, 阪本憲成, 小林亙, 尾上孝雄, 白川功, ``組込みシステム向けヘッドホンステレオ頭外音場拡大手法とその実装,'' 第17回 ディジタル信号処理シンポジウム, B2-4, November 2002.
[17]  河原 伸幸, 大谷 昌弘, 尾上 孝雄, 白川 功, ``IEEE802.11b を用いた映像伝送システムの設計,'' 第17回 ディジタル信号処理シンポジウム, B6-1, September 2002.
[18]  小坂篤史, 山口悟史, 奥畑宏之, 尾上孝雄, 白川功, ``組み込みCPUと専用回路によるOgg Vorbis音楽デコーダのVLSI化設計,'' 信学技報, SDM2002-159, ICD2002-70, pp. 37--42, August 2002.
[19]  谷 貞宏, 内田 好弘, 築山 修治, 白川 功, ``配線間容量モデル化とその評価について,'' 信学技報 DSP2002-83, pp. 7--12, June 2002.
[20]  岡田 勉, 内田 翼, 尾上 孝雄, 白川 功, ``次世代衛星航法システム受信機のための擬似雑音符号生成器の構成,'' 信学技報 DSP2002-69, pp. 19--24, June 2002.
[21]  宋 学燮, Alten-Erdene Shiitev, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4ビデオ符号化におけるエラー隠蔽アルゴリズムの提案,'' 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pp. 95--100, April 2002.
[22]  中川 克哉, 川北 将, 佐藤 康二, 花田 恵太郎, 千葉 徹, 白川 功, ``異機種間適応型オブジェクト共有環境,'' 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pp. 161--166, April 2002.
[23]  水野 洋, 小林 弘幸, 尾上 孝雄, 白川 功, ``組込みシステムアーキテクチャレベルにおける消費電力見積り手法,'' 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pp. 435--440, April 2002.
[24]  中川 貴史, 濱中 慎介, 肖 云和, 藤田 玄, 白川 功, ``MPEG-4 コア・プロファイル・コーデックの VLSI アーキテクチャ,'' 信学技報, VLD2001-136, pp. 31--38, January 2002.
[25]  木村 基, 三木 裕介, 尾上 孝雄, 白川 功, ``組込みシステム向け Java 実行環境の構築,'' 信学技報, VLD2001-137, pp. 39--44, January 2002.
[26]  大谷 昌弘, 河原 伸幸, 戸丸 知信, 丸山 一人, 尾上 孝雄, 白川 功, ``映像伝送システムのための誤り訂正ブロック単位 ARQ 手法,'' 第16回 ディジタル信号処理シンポジウム, C8-6, pp. 711--717, November 2001.
[27]  大谷 昌弘, 河原 伸幸, 中岡 弘幸, 戸丸 知信, 丸山 一人, 尾上 孝雄, 白川 功, ``データフレーム選択再送手法に基づいた映像伝送システムの設計,'' 信学技報, VLD2001-93, pp. 25--30, November 2001.
[28]  中川克哉, 佐藤康二, 津森靖, 花田恵太郎, 白川功, ``任意ネットワーク対応オブジェクトコミュニケーション環境 (OCEAN),'' 情報処理学会 第 104 回 マルチメディアと分散処理(石切)研究会, pp. 19--24, September 2001.
[29]  宋 学燮, Altan-Erdene Shiitev, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4 ビデオ伝送に対するエラー隠蔽アルゴリズムおよびアーキテクチャ,'' 信学技報, CAS2001-10, pp. 71--77, June 2001.
[30]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``ブロック暗号の高速化暗号モードとその VLSI 化設計,'' 信学技報, CAS2001-41, pp. 89--94, June 2001.
[31]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``3 次元音像定位リアルタイムアルゴリズムの DSP 実装とその評価,'' 信学技報, CAS2001-50, pp. 147--154, June 2001.
[32]  藤田 玄, 樽家 昌也, 本谷 謙治, 奥畑 宏之, 白川 功, ``顔オブジェクトのリアルタイム抽出アルゴリズム,'' 信学技報 DSP2001-31, pp. 87--92, June 2001.
[33]  三木 裕介, 坂本 守, 武内 良典, 吉田 豊彦, 白川 功, ``組込みシステム向きプロセッサのコード効率に関する評価,'' 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 113--118, April 2001.
[34]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A New Approach for 128-Bit Block Ciphers,'' In 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 231--236, April 2001.
[35]  宋 天, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``H.263 Version2 コーデックコアの VLSI 化設計,'' 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 561--566, April 2001.
[36]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``モノラル音の実時間 3 次元音像定位アルゴリズムの 1 チップ DSP 実装,'' 信学会 第 15 回ディジタル信号処理シンポジウム C6-2, pp. 599--604, November 2000.
[37]  宋 学燮, 宋 天, 岡田 浩行, 藤田 玄, 尾上 孝雄, 白川 功, ``動き検出を利用した MPEG-4 ビデオにおけるエラー隠蔽アルゴリズムの提案,'' 信学技報, DSP2000-107, pp. 37--43, October 2000.
[38]  宋 天, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``H.263 拡張 INTRA 符号化モードのコーデックとその VLSI とその VLSI アーキテクチャ,'' 信学技報, DSP2000-108, pp. 45--50, October 2000.
[39]  中川 克哉, 川北 将, 佐藤 康二, 水口 充, 白川 功, ``異機種間オブジェクトコミュニケーション環境,'' マルチメディア, 分散, 協調とモバイル(DICOMO 2002) シンポジウム, pp. 197--200, July 2000.
[40]  小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``3 次元音像定位リアルタイムアルゴリズムとその低消費電力 DSP 実装,'' 信学技報, CAS2000-13, pp. 97--102, June 2000.
[41]  黒田 涼, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4 向け省面積 SA-DCT の VLSI 化設計,'' 信学技報, CAS2000-14, pp. 103--108, June 2000.
[42]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いたハードウェア向き暗号方式,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 367--372, April 2000.
[43]  山田 昇平, 三木 Morgan 裕介, 藤田 玄, 尾上 孝雄, 白川 功, ``低ビットレート動画像符号化 VLSI 実装向きビットレート制御,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 385--390, April 2000.
[44]  丹羽 章雅, 橋本 晋弥, 奥畑 宏之, 尾上 孝雄, 白川 功, ``携帯用 MPEG-4 オーディオデコーダの VLSI 化設計,'' 第14回ディジタル信号処理シンポジウム, pp. 629--634, November 1999.
[45]  Zaldy ANDALES, 密山 幸男, 浅利 康二, 尾上 孝雄, 白川 功, ``リコンフィグラブルハードウェアを用いた暗号システム,'' 信学技報, CAS99-63, NLP99-87, pp. 7--14, September 1999.
[46]  古家 眞, 宋 宝玉, 吉田 幸弘, 尾上 孝雄, 白川 功, ``4相NMOSダイナミックロジック用アレイセル,'' 信学技報, CAS99-62, pp. 1--6, September 1999.
[47]  三木 Morgan 裕介, 山田 昇平, 藤田 玄, 尾上 孝雄, 白川 功, ``携帯端末用 H.263 動画像コーデックの VLSI 設計,'' DA シンポジウム 99, pp. 183--188, July 1999.
[48]  古家 眞, 松村 謙次, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘, ``医療用監視システムのための通信制御用LSI,'' 信学技報, CAS99, pp. 15--19, June 1999.
[49]  大卷 ロベルト 裕治, 藤田 玄, 尾上 孝雄, 白川 功, ``離散ウエーブレット変換に基づく動画像符号化器のアーキテクチャ,'' 信学技報, CAS99-33, pp. 21--28, June 1999.
[50]  藤嶋 秀幸, 竹本 裕介, 米田友和, 尾上 孝雄, 白川 功, ``動画像復号化と3次元グラフィックスで共用可能なメディアプロセッサ向き演算モジュールの設計,'' 信学技報, VLD98-41, pp. 31--38, September 1998.
[51]  滝大輔, M.H. Miki, 藤田玄, 尾上孝雄, 白川功, 藤原融, 嵩忠雄, ``再帰的最尤復号アルゴリズムを用いた誤り訂正復号器の VLSI 設計,'' 信学技報, VLD98-52, pp. 57--62, September 1998.
[52]  密山 幸男, 浅利 康二, 尾上 孝雄, 白川 功, 馬場 孝明, 大槻 達男, ``強誘電体メモリを用いた Reconfigurable Logic とその性能評価,'' 信学技報, ICD98-120, pp. 53--58, August 1998.
[53]  竹本 裕介, 米田 友和, 藤嶋 秀幸, 尾上 孝雄, 白川 功, ``テクスチャマッピングおよび動き補償用共有回路の VLSI 化設計,'' 信学技報, VLD98-33, pp. 19--26, July 1998.
[54]  三木裕介, 藤田玄, 奥畑宏之, 尾上孝雄, 白川功, ``携帯端末用 H.324 符号化/復号化方式とその VLSI 化設計,'' 信学会 第11回回路とシステム軽井沢ワークショップ, pp. 439--444, April 1998.
[55]  竹本裕介, 藤嶋秀幸, 尾上孝雄, 白川功, ``動画像復号化と3次元コンピュータグラフィクス向き行列ベクトル乗算器のアーキテクチャ,'' 信学会 第11回回路とシステム軽井沢ワークショップ, pp. 451--456, April 1998.
[56]  奥畑宏之, 三木裕介 Morgan, 尾上孝雄, 白川功, ``低ビットレート音声符号化用DSPのVLSI化設計,'' 第12回ディジタル信号処理シンポジウム, pp. 651-655, November 1997.
[57]  藤嶋秀幸, 竹本裕介, 尾上孝雄, 白川功, ``動画像と3次元CGを扱うメディアプロセッサのアーキテクチャに関す る研究,'' 第2回映像メディア処理シンポジウム, pp. 23-24, October 1997.
[58]  宮野鼻晃士, 藤田玄, 柳田和弘, 尾上孝雄, 白川 功, ``携帯環境向き低ビットレート動画像通信システムのVLSI 化設計,'' 電子情報通信学会技術研究報告, DSP97-107, vol. 97, no. 315, pp. 17-24, October 1997.
[59]  藤田 玄, 三木 裕介 Morgan, 尾上 孝雄, 白川 功, ``携帯端末用 H.263 符号化/復号化 VLSI の設計,'' 第12回画像符号化シンポジウム, pp. 51-52, October 1997.
[60]  澤卓, 長尾明, 白川功, 神戸尚志, 千原國宏, ``方形パッキング手法による MMIC 向き配置配線手法,'' 電子情報通信学会技術研究報告, VLD97-97, FTS97-60, pp. 141-146, October 1997.
[61]  澤卓, 長尾明, 神戸尚志, 白川功, 千原國宏, ``方形パッキング法の一算法,'' 電子情報通信学会技術研究報告, DSP97-53, pp. 159-166, June 1997.
[62]  長尾明, 澤卓, 磯部雅哉, 神戸尚志, 白川功, ``マイクロ波集積回路向きレイアウト設計に対する自動化手法,'' 電子情報通信学会第10回回路とシステム軽井沢ワークショップ, pp. 433-438, April 1997.
[63]  宮野鼻晃士, 藤田玄, 尾上孝雄, 白川功, ``低ビットレート画像符号化アルゴリズムとその VLSI 化設計,'' 電子情報通信学会技術研究報告, DSP96-89, vol. 96, no. 301, pp. 33-38, October 1996.
[64]  森川俊, 岡田圭介, 竹内澄高, 白川功, ``高性能定係数FIRフィルタのVLSI化設計,'' 情報処理学会DAシンポジウム'96, pp. 41-46, August 1996.
[65]  佐藤洋, 森本康夫, 正城敏博, 尾上孝雄, 白川功, ``1チップ MPEG2 デコーダの設計と動き補償器の VLSI 実装,'' 情報処理学会DAシンポジウム'96, pp. 47-52, August 1996.
[66]  森川俊, 岡田圭介, 竹内澄高, 白川功, ``ディジタル映像伝送向け高性 能FIRフィルタのVLSI化設計,'' 電子情報通信学会第9回回路とシステム軽 井沢ワークショップ, pp. 359-364, April 1996.
大会等発表論文
[1]  高橋 真吾, 築山 修治, 橋本 昌宜, 白川 功, ``液晶ディスプレイ用サンプリング回路の設計手法について,'' 2005 年電子情報通信学会ソサイエティ大会講演論文集, A-3-4, 2005.
[2]  重信優也, 尾上孝雄, 白川功, ``MPEG-2符号化情報に基づくMPEG-2/MPEG-4トランスコーディングの一手法,'' 電子情報通信学会 第19回信号処理シンポジウム, D4-4, November 2004.
[3]  今仲隆晃, 藤田玄, 尾上孝雄, 白川功, ``携帯端末向けリアルタイム人オブジェクト抽出,'' 第19回信号処理シンポジウム, D1-3, November 2004.
[4]  小坂 篤史, 奥畑 宏之, 尾上 孝雄, 白川 功, ``組込み向けOgg Vorbis デコーダシステムの設計,'' 電子情報通信学会 第19回信号処理シンポジウム, C7-1, November 2004.
[5]  渡邊 賢治, 西田 秀治, 藤田 玄, 尾上 孝雄, 白川 功, ``エージェント技術に基づくホームネットワーク制御システム,'' 電子情報通信学会ソサイエティ大会, A-1-30, September 2004.
[6]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶に適した配線間容量抽出の検討,'' 電子情報通信学会ソサイエティ大会, A-1-16, September 2004.
[7]  奥畑 宏之, 小坂 篤史, 松村 友哉, 尾上 孝雄, 白川 功, ``Retinex 輝度補正のリアルタイム動画像向け演算量削減手法,'' 電子情報通信学会ソサイエティ大会, A-4-22, September 2004.
[8]  川北将, 藤田玄, 尾上孝雄, 白川功, ``リアルタイム JPEG - MPEG-4 トランス コーダの実装,'' 信学会 総合大会, A-4-7, March 2004.
[9]  Y. D. Handoko, 宋天, 藤田玄, 尾上孝雄, 白川功, ``低演算量 H.264 向け動き検出アルゴリズム TS-ME の VLSI 化設計,'' 信学会 総合大会, A-4-10, March 2004.
[10]  中川 克哉, 川北 将, 尾上孝雄, 千葉 徹, 白川 功, ``適合的情報空間連係の利便性の考察,'' 情報処理学会 第2回 情報科学技術フォーラム(FIT2003), vol. 4, pp. 267--268, September 2003.
[11]  木村 基, 密山 幸男, 尾上 孝雄, 白川 功, ``無線 LAN セキュリティ拡張規格向け暗号処理器のアーキテクチャ,'' 電子情報通信学会ソサイエティ大会, A-4-4, September 2003.
[12]  今仲 隆晃, 本谷 謙治, 藤田 玄, 尾上 孝雄, 白川 功, ``顔領域に基づく携帯端末向けリアルタイム髪オブジェクト抽出,'' 電子情報通信学会ソサイエティ大会, A-4-26, September 2003.
[13]  前田真一, 山口悟史, 小坂篤史, 奥畑宏之, 山田晃久, 尾上孝雄, 白川功, ``Bach C言語によるOgg VorbisデコーダのVLSI化設計,'' 信学会 総合大会, A-3-8, March 2003.
[14]  岩永信之, 阪本憲成, 小林亙, 尾上孝雄, 白川功, ``ヘッドホンステレオ頭外音場拡大手法の組込み実装,'' 信学会 ソサイエティ大会, A-4-20, September 2002.
[15]  内田 翼, 岡田 勉, 尾上 孝雄, 白川 功, ``次世代衛星航法システム対応汎用擬似雑音符号生成器の実装,'' 信学会 ソサイエティ大会, A-5-15, September 2002.
[16]  伊勢 正尚, 内田 好弘, 尾上 孝雄, 白川 功, ``W-CDMA 用階層化ディジタルマッチトフィルタ,'' 信学会 ソサイエティ大会, A-1-7, September 2001.
[17]  内田 好弘, 伊勢 正尚, 尾上 孝雄, 白川 功, ``W-CDMA ターボ符号処理向け VLSI アーキテクチャ,'' 信学会 ソサイエティ大会, A-1-8, September 2001.
[18]  三木 裕介, 坂本 守, 河原 伸幸, 武内 良典, 吉田 豊彦, 白川 功, ``組込みシステム用実行ファイルの効率的圧縮および実行方法の提案,'' 信学会 ソサイエティ大会, A-3-15, September 2001.
[19]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``モノラル音 3 次元音像定位処理システムのハードウェア実装,'' 信学会 ソサイエティ大会, A-4-40, September 2001.
[20]  中川 貴史, 濱中 慎介, 藤田 玄, 白川 功, ``MPEG-4 動き補償用パディング処理の VLSI 化設計,'' 信学会 ソサイエティ大会, A-4-41, September 2001.
[21]  小林 弘幸, 水野 洋, 尾上 孝雄, 白川 功, ``組込みシステムにおける消費電力見積りの一手法,'' 信学会 ソサイエティ大会, SA-1-1, September 2001.
[22]  Altan-Erdene Shiitev, 岡田 浩行, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``電子透かしを用いた MPEG-4 ビデオ伝送におけるエラー検出方式の検討,'' 信学会 ソサイエティ大会, D-11-38, September 2001.
[23]  岡田 浩行, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4 ビデオ符号化における電子透かしを利用したエラー検出方式,'' 2001 画像電子学会年次大会一般セッション, pp. 19--20, June 2001.
[24]  Gulistan Raja, 宋 天, 藤田 玄, 尾上 孝雄, 白川 功, ``H.263 向きデブロッキングフィルタおよび拡張 Intra 符号化処理の VLSI 化設計,'' 信学会 総合大会, A-3-7, March 2001.
[25]  山口 悟史, 小坂 篤史, 奥畑 宏之, 白川 功, ``組み込み CPU 向け Ogg Vorbis デコーダの VLSI 実装,'' 信学会 総合大会, A-3-8, March 2001.
[26]  小俣 真也, 阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``3 次元音像移動アルゴリズムの DSP 実装,'' 信学会 総合大会, A-4-55, March 2001.
[27]  密山 幸男, 岩永 信之, 尾上 孝雄, 白川 功, ``Bluetooth スキャッタネットの構築手法と経路制御,'' 信学会 総合大会, A-4-68, March 2001.
[28]  本谷 謙治, 藤田 玄, 白川 功, ``改良 SNAKES による顔オブジェクト高速抽出手法,'' 信学会 総合大会, D-12-15, March 2001.
[29]  小俣 真也, 小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``汎用 DSP 実装用 3 次元音像定位リアルタイムアルゴリズム,'' 映像情報メディア学会 冬季大会, 1-11, December 2000.
[30]  三木 裕介, 尾上 孝雄, 白川 功, ``組込みプロセッサ向け Java アクセラレータの VLSI 化設計,'' 信学会 ソサイエティ大会, A-3-12, October 2000.
[31]  小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``3 次元音像定位のための実時間アルゴリズム,'' 信学会 ソサイエティ大会, A-4-23, October 2000.
[32]  濱中 慎介, 黒田 涼, 藤田 玄, 白川 功, ``MPEG-4 リバーシブル可変長復号器の VLSI 化設計,'' 信学会 ソサイエティ大会, A-4-41, October 2000.
[33]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いた暗号方式,'' 信学会 ソサイエティ大会, A-4-42, October 2000.
[34]  橋本 晋弥, 丹羽 章雅, 奥畑 宏之, 尾上 孝雄, 白川 功, ``MPEG-4 オーディオデコーダにおけるノイズレス復号器およびスペクトル 予測器の VLSI 化設計,'' 信学会 ソサイエティ大会, A-3-4, September 1999.
[35]  大下勝, 尾上孝雄, 白川功, ``JBIG 算術符号化部の高速化設計,'' 信学会 総合大会, A-4-32, March 1999.
[36]  山田昇平, 三木 Morgan 裕助, 藤田玄, 尾上 孝雄, 白川 功, ``H.263 符号化におけるビットレート制御に関する研究,'' 信学会 ソサイエティ大会, B-8-31, October 1998.
[37]  竹本 裕介, 藤嶋 秀幸, 尾上 孝雄, 白川 功, ``画像符号化と3次元CGで共用可能な行列・ベクトル乗算器,'' 信学会 総合大会, C-12-19, May 1998.
[38]  藤田玄, 尾上孝雄, 白川功, ``H.263用 DCT/IDCT演算コアのVLSI化設計,'' 電子情報通信学会ソサイエティ大会, C-12-28, August 1997.
[39]  宮野鼻晃士, 柳田和弘, 尾上孝雄, 白川功, ``低ビットレート動画像通信システムのVLSI化設計,'' SCI第41回システム制御情報学会研究発表講演会, pp. 247-248, May 1997.
[40]  森川俊, 岡田圭介, 竹内澄高, 白川功, ``映像伝送用高性能ディジタルフィルタの VLSI 化設計,'' 電子情報通信学会総合大会, A-4-29, March 1997.
[41]  藤田玄, Itthichai Arungsrisangchai, 尾上孝雄, 白川功, ``H.263 向け動き検出器の VLSI 化設計,'' 電子情報通信学会総合大会, SC-11-2, March 1997.
[42]  吉田幸宏, 宋宝玉, 奥畑宏之, 尾上孝雄, 白川功, ``組み込み用プロセッサの低消費電力化に対する一手法,'' 電子情報 通信学会ソサイアティ大会, SA-1-2, September 1996.

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