論文誌
[1]  H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518--2529, December 2014.
[2]  M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' IEICE Trans. on Information and Systems , vol. E91-D, no. 3, pp. 655--660, March 2008.
[3]  M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2661-2668, December 2007.
[4]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling,'' IEICE Trans. on Electronics, vol. E90-C, no. 6, pp. 1267-1273, June 2007.
[5]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560--3568, December 2006.
[6]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[7]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[8]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3375-3381, December 2005.
[9]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3564-3572, December 2005.
[10]  T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment for Minimizing Supply Voltage Drop,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3429-3436, December 2005.
[11]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E88-A, no. 4, pp. 885-891, April 2005.
[12]  T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' IEICE Trans. on Electronics, vol. E88-C, no. 3, pp. 437-444, March 2005.
[13]  M. Hashimoto and H. Onodera, ``Crosstalk Noise Optimization by Post-Layout Transistor Sizing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E87-A, no. 12, pp. 3251-3257, December 2004.
[14]  M. Hashimoto, Y. Yamada, and H. Onodera, ``Equivalent Waveform Propagation for Static Timing Analysis,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 23, no. 4, pp. 498-508, April 2004.
国際会議
[1]  R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, ``Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
[2]  N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi Author(s) in English , ``A Novel Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch (2v-1cas) for Nonvolatile Crossbar Switch with Multiple Fan-Outs,'' Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 32--35, December 2015.
[3]  M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 14--15, January 2015.
[4]  D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 313-316, November 2013.
[5]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227--230, May 2006.
[6]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction,'' In The 3rd International Workshop on Compact Modeling, pp. 51--56, January 2006.
[7]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Interconnect Rl Extraction at a Single Representative Frequency,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 515-520, January 2006.
[8]  T. Kouno, M. Hashimoto, and H. Onodera, ``Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 453-456, November 2005.
[9]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip High-Throughput Global Signaling,'' In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 79-82, October 2005.
[10]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 613-616, September 2005.
[11]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), May 2005.
[12]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics,'' In Proceedings of International Meeting for Future of Electron Devices, Kansai, pp. 33-34, April 2005.
[13]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Effects of On-Chip Inductance on Power Distribution Grid,'' In Proceedings of International Symposium on Physical Design (ISPD), pp. 63-69, April 2005.
[14]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation in H-Tree Structure,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 402-407, March 2005.
[15]  T. Sato, M. Hashimoto, and H. Onodera, ``Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 723-728, January 2005.
[16]  M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1098-1101, January 2005.
[17]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Return Path Selection for Loop Rl Extraction,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1078-1081, January 2005.
[18]  A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um Cmos Process,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), p. D9-D10, January 2005.
[19]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip Global Signaling,'' In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) , pp. 87-100, November 2004.
[20]  M. Hashimoto, J. Yamaguchi, and H. Onodera, ``Timing Analysis Considering Spatial Power/Ground Level Variation,'' In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 814-820, November 2004.
[21]  M. Hashimoto, A. Tsuchiya, and H. Onodera, ``On-Chip Global Signaling by Wave Pipelining,'' In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 311-314, October 2004.
[22]  A. Muramatsu, M. Hashimoto, and H. Onodera, ``Lsi Power Network Analysis with On-Chip Wire Inductance,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 55-60, October 2004.
[23]  T. Sato, M. Hashimoto, and H. Onodera, ``An Ir-Drop Minimization by Optimizing Number and Location of Power Supply Pads,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 66-72, October 2004.
[24]  M. Hashimoto, T. Yamamoto, and H. Onodera, ``Statistical Analysis of Clock Skew Variation,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 214-219, October 2004.
[25]  T. Miyazaki, M. Hashimoto, and H. Onodera, ``A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll,'' In IEEJ International Analog VLSI Workshop, pp. 45-50, October 2004.
[26]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 489-492, September 2004.
[27]  A. Shinmyo, M. Hashimoto, and H. Onodera, ``Design and Optimization of Cmos Current Mode Logic Dividers,'' In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits , pp. 434-435, August 2004.

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