論文誌
[1]  H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518--2529, December 2014.
[2]  H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1468--1482, July 2014.
[3]  H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Nbti Mitigation Method by Inputting Random Scan-In Vectors in Standby Time,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1483--1491, July 2014.
[4]  D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, vol. 21, no. 12, p. 2165 -- 2178, December 2013.
[5]  T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices,'' IEICE Trans. on Information and Systems , vol. E96-D, no. 8, pp. 1624--1631, August 2013.
[6]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating NBTI-Induced Delay Degradation,'' IEICE Trans. Fundamentals, vol. E94-A, no. 12, pp. 2545-2553, December 2011.
国際会議
[1]  M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 14--15, January 2015.
[2]  Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, and Takao Onoye, ``Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design,'' In ReConFig, December 2013.
[3]  D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 313-316, November 2013.
[4]  T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.
[5]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures,'' In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pp. 189-194, September 2011.
[6]  Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, and Takao Onoye, ``Nbti Mitigation by Giving Random Scan-In Vectors during Standby Mode,'' In PATMOS2011, September 2011.
[7]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 646-651, March 2010.
[8]  D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.
研究会等発表論文
[1]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討,'' 信学技報, RECONF2013-8, vol. 113, no. 52, pp. 41-46, May 2013.
[2]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的部分再構成による故障回避に関する一考察,'' 信学技報, RECONF2012-59 , vol. 112, no. 325, pp. 71-76, November 2012.
[3]  亀田 敏広, 郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``スキャンパスを用いたNBTI劣化抑制に関する研究,'' 情報処理学会DAシンポジウム, pp. 201-206, August 2011.
[4]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的再構成可能アーキテクチャによる故障回避機構の定量的評価,'' 信学技報, RECONF2011-6, vol. 111, no. 31, pp. 31-36, May 2011.
[5]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``NBTI による劣化予測におけるトランジスタ動作確率算出法の評価,'' 情報処理学会DAシンポジウム, pp. 181-186, August 2009.

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