論文誌
[1]  H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, ``An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion,'' IEEE Transactions on Circuits and Systems II, vol. 58, no. 5, pp. 299--303, May 2011.
国際会議
[1]  S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, ``Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 107-114, November 2013. (San Jose)
[2]  D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, ``A 16-Bit Risc Processor with 4.18pj/Cycle at 0.5v Operation,'' In Proceedings of IEEE COOL Chips, p. 190, April 2010.
[3]  R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa, ``Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 811--814, July 2000.
研究会等発表論文
[1]  黒田 弾, 更田 裕司, 橋本 昌宜, 尾上 孝雄, ``低エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価,'' 情報処理学会第141回システムLSI設計技術研究会, pp107-112, October 2009.
[2]  黒田 涼, 藤田 玄, 尾上 孝雄, 白川 功, ``MPEG-4 向け省面積 SA-DCT の VLSI 化設計,'' 信学技報, CAS2000-14, pp. 103--108, June 2000.
大会等発表論文
[1]  濱中 慎介, 黒田 涼, 藤田 玄, 白川 功, ``MPEG-4 リバーシブル可変長復号器の VLSI 化設計,'' 信学会 ソサイエティ大会, A-4-41, October 2000.

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